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fb70343484
In our real world application, we found the following optimization is missed in DAGCombiner (zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst)) If the user of original zext is an add, it may enable further lea optimization on x86. This patch add a new function CombineZExtLogicopShiftLoad to do this optimization. Differential Revision: https://reviews.llvm.org/D44402 llvm-svn: 329516
15 lines
257 B
LLVM
15 lines
257 B
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu < %s -o - | FileCheck %s
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define i32 @test1(i8* %p) {
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; CHECK: ldrb
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; CHECK-NEXT: ubfx
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; CHECK-NEXT: ret
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%1 = load i8, i8* %p
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%2 = lshr i8 %1, 1
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%3 = and i8 %2, 1
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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