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5f15092063
This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for new instructions (except vector 32-bit float and 128-bit float). - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of z14 as host processor. Support for the new 32-bit vector float and 128-bit vector float instructions is provided by separate patches. llvm-svn: 308194
57 lines
1.1 KiB
LLVM
57 lines
1.1 KiB
LLVM
; Test indirect jumps on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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define i32 @f1(i32 %x, i32 %y, i32 %op) {
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; CHECK-LABEL: f1:
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; CHECK: ahi %r4, -1
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; CHECK: clibh %r4, 5, 0(%r14)
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; CHECK: llgfr [[OP64:%r[0-5]]], %r4
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; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3
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; CHECK: larl [[BASE:%r[1-5]]]
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; CHECK: bi 0([[BASE]],[[INDEX]])
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entry:
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switch i32 %op, label %exit [
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i32 1, label %b.add
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i32 2, label %b.sub
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i32 3, label %b.and
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i32 4, label %b.or
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i32 5, label %b.xor
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i32 6, label %b.mul
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]
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b.add:
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%add = add i32 %x, %y
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br label %exit
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b.sub:
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%sub = sub i32 %x, %y
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br label %exit
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b.and:
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%and = and i32 %x, %y
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br label %exit
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b.or:
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%or = or i32 %x, %y
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br label %exit
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b.xor:
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%xor = xor i32 %x, %y
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br label %exit
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b.mul:
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%mul = mul i32 %x, %y
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br label %exit
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exit:
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%res = phi i32 [ %x, %entry ],
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[ %add, %b.add ],
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[ %sub, %b.sub ],
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[ %and, %b.and ],
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[ %or, %b.or ],
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[ %xor, %b.xor ],
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[ %mul, %b.mul ]
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ret i32 %res
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}
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