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b483140318
This patch moves formation of LOC-type instructions from (late) IfConversion to the early if-conversion pass, and in some cases additionally creates them directly from select instructions during DAG instruction selection. To make early if-conversion work, the patch implements the canInsertSelect / insertSelect callbacks. It also implements the commuteInstructionImpl and FoldImmediate callbacks to enable generation of the full range of LOC instructions. Finally, the patch adds support for all instructions of the load-store-on-condition-2 facility, which allows using LOC instructions also for high registers. Due to the use of the GRX32 register class to enable high registers, we now also have to handle the cases where there are still no single hardware instructions (conditional move from a low register to a high register or vice versa). These are converted back to a branch sequence after register allocation. Since the expandRAPseudos callback is not allowed to create new basic blocks, this requires a simple new pass, modelled after the ARM/AArch64 ExpandPseudos pass. Overall, this patch causes significantly more LOC-type instructions to be used, and results in a measurable performance improvement. llvm-svn: 288028
126 lines
2.8 KiB
LLVM
126 lines
2.8 KiB
LLVM
; Test LOCR and LOCGR.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -verify-machineinstrs | FileCheck %s
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;
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; Run the test again to make sure it still works the same even
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; in the presence of the load-store-on-condition-2 facility.
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs | FileCheck %s
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; Test LOCR.
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define i32 @f1(i32 %a, i32 %b, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK: clfi %r4, 42
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; CHECK: locrhe %r2, %r3
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%res = select i1 %cond, i32 %a, i32 %b
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ret i32 %res
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}
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; Test LOCGR.
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define i64 @f2(i64 %a, i64 %b, i64 %limit) {
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; CHECK-LABEL: f2:
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; CHECK: clgfi %r4, 42
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; CHECK: locgrhe %r2, %r3
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; CHECK: br %r14
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%cond = icmp ult i64 %limit, 42
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Test LOCR in a case that could use COMPARE AND BRANCH. We prefer using
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; LOCR if possible.
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define i32 @f3(i32 %a, i32 %b, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK: chi %r4, 42
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; CHECK: locrlh %r2, %r3
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; CHECK: br %r14
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%cond = icmp eq i32 %limit, 42
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%res = select i1 %cond, i32 %a, i32 %b
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ret i32 %res
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}
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; ...and again for LOCGR.
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define i64 @f4(i64 %a, i64 %b, i64 %limit) {
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; CHECK-LABEL: f4:
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; CHECK: cghi %r4, 42
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; CHECK: locgrlh %r2, %r3
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; CHECK: br %r14
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%cond = icmp eq i64 %limit, 42
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Check that we also get LOCR as a result of early if-conversion.
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define i32 @f5(i32 %a, i32 %b, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK: clfi %r4, 41
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; CHECK: locrh %r2, %r3
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; CHECK: br %r14
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entry:
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%cond = icmp ult i32 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ %a, %if.then ], [ %b, %entry ]
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ret i32 %res
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}
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; ... and likewise for LOCGR.
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define i64 @f6(i64 %a, i64 %b, i64 %limit) {
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; CHECK-LABEL: f6:
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; CHECK: clgfi %r4, 41
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; CHECK: locgrh %r2, %r3
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; CHECK: br %r14
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entry:
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%cond = icmp ult i64 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i64 [ %a, %if.then ], [ %b, %entry ]
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ret i64 %res
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}
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; Check that inverting the condition works as well.
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define i32 @f7(i32 %a, i32 %b, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK: clfi %r4, 41
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; CHECK: locrle %r2, %r3
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; CHECK: br %r14
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entry:
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%cond = icmp ult i32 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i32 [ %b, %if.then ], [ %a, %entry ]
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ret i32 %res
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}
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; ... and likewise for LOCGR.
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define i64 @f8(i64 %a, i64 %b, i64 %limit) {
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; CHECK-LABEL: f8:
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; CHECK: clgfi %r4, 41
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; CHECK: locgrle %r2, %r3
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; CHECK: br %r14
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entry:
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%cond = icmp ult i64 %limit, 42
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br i1 %cond, label %if.then, label %return
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if.then:
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br label %return
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return:
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%res = phi i64 [ %b, %if.then ], [ %a, %entry ]
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ret i64 %res
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}
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