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llvm-mirror/test/CodeGen/SystemZ/fp-cmp-06.ll
Ulrich Weigand bc658bf60a [SystemZ] Add support for IBM z14 processor (3/3)
This adds support for the new 128-bit vector float instructions of z14.
Note that these instructions actually only operate on the f128 type,
since only each 128-bit vector register can hold only one 128-bit
float value.  However, this is still preferable to the legacy 128-bit
float instructions, since those operate on pairs of floating-point
registers (so we can hold at most 8 values in registers), while the
new instructions use single vector registers (so we hold up to 32
value in registers).

Adding support includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions.  This includes allocating the f128
  type now to the VR128BitRegClass instead of FP128BitRegClass.
- Scheduler description support for the instructions.

Note that for a small number of operations, we have no new vector
instructions (like integer <-> 128-bit float conversions), and so
we use the legacy instruction and then reformat the operand
(i.e. copy between a pair of floating-point registers and a
vector register).

llvm-svn: 308196
2017-07-17 17:44:20 +00:00

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1.0 KiB
LLVM

; Test f128 comparisons on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; There is no memory form of 128-bit comparison.
define i64 @f1(i64 %a, i64 %b, fp128 *%ptr1, fp128 *%ptr2) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r4)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r5)
; CHECK: wfcxb [[REG1]], [[REG2]]
; CHECK-NEXT: locgrne %r2, %r3
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%cond = fcmp oeq fp128 %f1, %f2
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}
; Check comparison with zero -- it is not worthwhile to copy to
; FP pairs just so we can use LTXBR, so simply load up a zero.
define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
; CHECK-LABEL: f2:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r4)
; CHECK-DAG: vzero [[REG2:%v[0-9]+]]
; CHECK: wfcxb [[REG1]], [[REG2]]
; CHECK-NEXT: locgrne %r2, %r3
; CHECK: br %r14
%f = load fp128, fp128 *%ptr
%cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
%res = select i1 %cond, i64 %a, i64 %b
ret i64 %res
}