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ee0d5cd952
This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195
44 lines
1.3 KiB
LLVM
44 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
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declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
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define double @f1(double %f1, double %f2, double %acc) {
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; CHECK-LABEL: f1:
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; CHECK: wfnmadb %f0, %f0, %f2, %f4
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; CHECK: br %r14
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%res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc)
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%negres = fsub double -0.0, %res
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ret double %negres
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}
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define double @f2(double %f1, double %f2, double %acc) {
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; CHECK-LABEL: f2:
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; CHECK: wfnmsdb %f0, %f0, %f2, %f4
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; CHECK: br %r14
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%negacc = fsub double -0.0, %acc
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%res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc)
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%negres = fsub double -0.0, %res
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ret double %negres
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}
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define float @f3(float %f1, float %f2, float %acc) {
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; CHECK-LABEL: f3:
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; CHECK: wfnmasb %f0, %f0, %f2, %f4
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; CHECK: br %r14
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%res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc)
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%negres = fsub float -0.0, %res
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ret float %negres
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}
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define float @f4(float %f1, float %f2, float %acc) {
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; CHECK-LABEL: f4:
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; CHECK: wfnmssb %f0, %f0, %f2, %f4
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; CHECK: br %r14
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%negacc = fsub float -0.0, %acc
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%res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc)
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%negres = fsub float -0.0, %res
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ret float %negres
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}
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