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961f3df27b
As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
57 lines
1.4 KiB
LLVM
57 lines
1.4 KiB
LLVM
; Test that divisions by constants are implemented as multiplications.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -asm-verbose=0 | FileCheck %s
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; Check signed 32-bit division.
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define i32 @f1(i32 %a) {
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; CHECK-LABEL: f1:
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; CHECK: lgfr [[REG:%r[0-5]]], %r2
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; CHECK: msgfi [[REG]], 502748801
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; CHECK-DAG: srlg [[RES1:%r[0-5]]], [[REG]], 63
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; CHECK-DAG: srag %r2, [[REG]], 46
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; CHECK: ar %r2, [[RES1]]
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; CHECK: br %r14
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%b = sdiv i32 %a, 139968
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ret i32 %b
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}
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; Check unsigned 32-bit division.
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define i32 @f2(i32 %a) {
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; CHECK-LABEL: f2:
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; CHECK: llgfr [[REG:%r[0-5]]], %r2
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; CHECK: msgfi [[REG]], 502748801
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; CHECK: srlg %r2, [[REG]], 46
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; CHECK: br %r14
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%b = udiv i32 %a, 139968
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ret i32 %b
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}
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; Check signed 64-bit division.
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define i64 @f3(i64 %dummy, i64 %a) {
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; CHECK-LABEL: f3:
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; CHECK-DAG: llihf [[CONST:%r[0-5]]], 1005497601
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; CHECK-DAG: oilf [[CONST]], 4251762321
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; CHECK-DAG: srag [[REG:%r[0-5]]], %r3, 63
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; CHECK-DAG: ngr [[REG]], [[CONST]]
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; CHECK-DAG: mlgr %r2, [[CONST]]
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; CHECK: sgr %r2, [[REG]]
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; CHECK: srlg [[RES1:%r[0-5]]], %r2, 63
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; CHECK: srag %r2, %r2, 15
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; CHECK: agr %r2, [[RES1]]
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; CHECK: br %r14
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%b = sdiv i64 %a, 139968
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ret i64 %b
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}
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; Check unsigned 64-bit division.
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define i64 @f4(i64 %dummy, i64 %a) {
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; CHECK-LABEL: f4:
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; CHECK: llihf [[CONST:%r[0-5]]], 1005497601
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; CHECK: oilf [[CONST]], 4251762321
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; CHECK: mlgr %r2, [[CONST]]
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; CHECK: srlg %r2, %r2, 15
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; CHECK: br %r14
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%b = udiv i64 %a, 139968
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ret i64 %b
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}
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