mirror of
https://github.com/RPCS3/llvm-mirror.git
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0c16dcd701
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO as well as ADDCARRY/SUBCARRY on top of the new CC implementation. In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead of the old ADDC/ADDE logic, which means we no longer need to use "glue" links for those instructions. This also allows making full use of the memory-based instructions like ALSI, which couldn't be recognized due to limitations in the DAG matcher previously. Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to directly using the ADD instructions and checking for a CC 3 result. llvm-svn: 331203
305 lines
9.5 KiB
LLVM
305 lines
9.5 KiB
LLVM
; Test additions between an i64 and a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Check ALGFR.
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define zeroext i1 @f1(i64 %dummy, i64 %a, i32 %b, i64 *%res) {
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; CHECK-LABEL: f1:
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; CHECK: algfr %r3, %r4
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check using the overflow result for a branch.
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define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%res) {
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; CHECK-LABEL: f2:
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; CHECK: algfr %r3, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: jgnle foo@PLT
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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br i1 %obit, label %call, label %exit
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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; ... and the same with the inverted direction.
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define void @f3(i64 %dummy, i64 %a, i32 %b, i64 *%res) {
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; CHECK-LABEL: f3:
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; CHECK: algfr %r3, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: jgle foo@PLT
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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br i1 %obit, label %exit, label %call
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call:
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tail call i64 @foo()
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br label %exit
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exit:
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ret void
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}
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; Check ALGF with no displacement.
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define zeroext i1 @f4(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f4:
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; CHECK: algf %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%b = load i32, i32 *%src
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check the high end of the aligned ALGF range.
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define zeroext i1 @f5(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f5:
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; CHECK: algf %r3, 524284(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r4, 524288
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; CHECK: algf %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check the high end of the negative aligned ALGF range.
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define zeroext i1 @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f7:
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; CHECK: algf %r3, -4(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check the low end of the ALGF range.
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define zeroext i1 @f8(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f8:
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; CHECK: algf %r3, -524288(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define zeroext i1 @f9(i64 %dummy, i64 %a, i32 *%src, i64 *%res) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r4, -524292
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; CHECK: algf %r3, 0(%r4)
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; CHECK-DAG: stg %r3, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check that ALGF allows an index.
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define zeroext i1 @f10(i64 %src, i64 %index, i64 %a, i64 *%res) {
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; CHECK-LABEL: f10:
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; CHECK: algf %r4, 524284({{%r3,%r2|%r2,%r3}})
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; CHECK-DAG: stg %r4, 0(%r5)
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; CHECK-DAG: ipm [[REG:%r[0-5]]]
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; CHECK-DAG: risbg %r2, [[REG]], 63, 191, 35
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32, i32 *%ptr
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%bext = zext i32 %b to i64
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%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %a, i64 %bext)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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store i64 %val, i64 *%res
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ret i1 %obit
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}
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; Check that additions of spilled values can use ALGF rather than ALGFR.
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define zeroext i1 @f11(i32 *%ptr0) {
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; CHECK-LABEL: f11:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: algf %r2, 160(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, i32 *%ptr0, i64 2
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%ptr2 = getelementptr i32, i32 *%ptr0, i64 4
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%ptr3 = getelementptr i32, i32 *%ptr0, i64 6
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%ptr4 = getelementptr i32, i32 *%ptr0, i64 8
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%ptr5 = getelementptr i32, i32 *%ptr0, i64 10
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%ptr6 = getelementptr i32, i32 *%ptr0, i64 12
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%ptr7 = getelementptr i32, i32 *%ptr0, i64 14
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%ptr8 = getelementptr i32, i32 *%ptr0, i64 16
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%ptr9 = getelementptr i32, i32 *%ptr0, i64 18
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%val0 = load i32, i32 *%ptr0
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%val1 = load i32, i32 *%ptr1
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%val2 = load i32, i32 *%ptr2
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%val3 = load i32, i32 *%ptr3
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%val4 = load i32, i32 *%ptr4
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%val5 = load i32, i32 *%ptr5
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%val6 = load i32, i32 *%ptr6
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%val7 = load i32, i32 *%ptr7
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%val8 = load i32, i32 *%ptr8
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%val9 = load i32, i32 *%ptr9
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%frob0 = add i32 %val0, 100
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%frob1 = add i32 %val1, 100
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%frob2 = add i32 %val2, 100
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%frob3 = add i32 %val3, 100
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%frob4 = add i32 %val4, 100
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%frob5 = add i32 %val5, 100
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%frob6 = add i32 %val6, 100
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%frob7 = add i32 %val7, 100
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%frob8 = add i32 %val8, 100
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%frob9 = add i32 %val9, 100
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store i32 %frob0, i32 *%ptr0
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store i32 %frob1, i32 *%ptr1
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store i32 %frob2, i32 *%ptr2
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store i32 %frob3, i32 *%ptr3
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store i32 %frob4, i32 *%ptr4
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store i32 %frob5, i32 *%ptr5
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store i32 %frob6, i32 *%ptr6
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store i32 %frob7, i32 *%ptr7
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store i32 %frob8, i32 *%ptr8
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store i32 %frob9, i32 *%ptr9
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%ret = call i64 @foo()
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%ext0 = zext i32 %frob0 to i64
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%ext1 = zext i32 %frob1 to i64
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%ext2 = zext i32 %frob2 to i64
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%ext3 = zext i32 %frob3 to i64
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%ext4 = zext i32 %frob4 to i64
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%ext5 = zext i32 %frob5 to i64
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%ext6 = zext i32 %frob6 to i64
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%ext7 = zext i32 %frob7 to i64
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%ext8 = zext i32 %frob8 to i64
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%ext9 = zext i32 %frob9 to i64
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%t0 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %ret, i64 %ext0)
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%add0 = extractvalue {i64, i1} %t0, 0
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%obit0 = extractvalue {i64, i1} %t0, 1
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%t1 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add0, i64 %ext1)
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%add1 = extractvalue {i64, i1} %t1, 0
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%obit1 = extractvalue {i64, i1} %t1, 1
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%res1 = or i1 %obit0, %obit1
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%t2 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add1, i64 %ext2)
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%add2 = extractvalue {i64, i1} %t2, 0
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%obit2 = extractvalue {i64, i1} %t2, 1
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%res2 = or i1 %res1, %obit2
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%t3 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add2, i64 %ext3)
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%add3 = extractvalue {i64, i1} %t3, 0
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%obit3 = extractvalue {i64, i1} %t3, 1
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%res3 = or i1 %res2, %obit3
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%t4 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add3, i64 %ext4)
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%add4 = extractvalue {i64, i1} %t4, 0
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%obit4 = extractvalue {i64, i1} %t4, 1
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%res4 = or i1 %res3, %obit4
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%t5 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add4, i64 %ext5)
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%add5 = extractvalue {i64, i1} %t5, 0
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%obit5 = extractvalue {i64, i1} %t5, 1
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%res5 = or i1 %res4, %obit5
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%t6 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add5, i64 %ext6)
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%add6 = extractvalue {i64, i1} %t6, 0
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%obit6 = extractvalue {i64, i1} %t6, 1
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%res6 = or i1 %res5, %obit6
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%t7 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add6, i64 %ext7)
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%add7 = extractvalue {i64, i1} %t7, 0
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%obit7 = extractvalue {i64, i1} %t7, 1
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%res7 = or i1 %res6, %obit7
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%t8 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add7, i64 %ext8)
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%add8 = extractvalue {i64, i1} %t8, 0
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%obit8 = extractvalue {i64, i1} %t8, 1
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%res8 = or i1 %res7, %obit8
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%t9 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %add8, i64 %ext9)
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%add9 = extractvalue {i64, i1} %t9, 0
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%obit9 = extractvalue {i64, i1} %t9, 1
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%res9 = or i1 %res8, %obit9
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ret i1 %res9
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}
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declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
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