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6cc38f3a79
Summary: Recognize RISBG opportunities where the end result is narrower than the original input - where a truncate separates the shift/and operations. The motivating case is some code in postgres which looks like: srlg %r2, %r0, 11 nilh %r2, 255 Reviewers: uweigand Author: RolandF Differential Revision: http://reviews.llvm.org/D21452 llvm-svn: 273433
119 lines
2.7 KiB
LLVM
119 lines
2.7 KiB
LLVM
; Test sequences that can use RISBG with a normal first operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a case with two ANDs.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: risbg %r2, %r3, 60, 62, 0
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; CHECK: br %r14
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%anda = and i32 %a, -15
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%andb = and i32 %b, 14
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%or = or i32 %anda, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: risbg %r2, %r3, 60, 62, 0
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; CHECK: br %r14
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%anda = and i64 %a, -15
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%andb = and i64 %b, 14
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%or = or i64 %anda, %andb
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ret i64 %or
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}
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; Test a case with two ANDs and a shift.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: risbg %r2, %r3, 60, 63, 56
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; CHECK: br %r14
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%anda = and i32 %a, -16
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%shr = lshr i32 %b, 8
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%andb = and i32 %shr, 15
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%or = or i32 %anda, %andb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: risbg %r2, %r3, 60, 63, 56
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; CHECK: br %r14
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%anda = and i64 %a, -16
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%shr = lshr i64 %b, 8
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%andb = and i64 %shr, 15
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%or = or i64 %anda, %andb
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ret i64 %or
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}
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; Test a case with a single AND and a left shift.
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define i32 @f5(i32 %a, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: risbg %r2, %r3, 32, 53, 10
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; CHECK: br %r14
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%anda = and i32 %a, 1023
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%shlb = shl i32 %b, 10
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%or = or i32 %anda, %shlb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f6(i64 %a, i64 %b) {
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; CHECK-LABEL: f6:
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; CHECK: risbg %r2, %r3, 0, 53, 10
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; CHECK: br %r14
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%anda = and i64 %a, 1023
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%shlb = shl i64 %b, 10
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%or = or i64 %anda, %shlb
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ret i64 %or
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}
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; Test a case with a single AND and a right shift.
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define i32 @f7(i32 %a, i32 %b) {
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; CHECK-LABEL: f7:
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; CHECK: risbg %r2, %r3, 40, 63, 56
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; CHECK: br %r14
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%anda = and i32 %a, -16777216
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%shrb = lshr i32 %b, 8
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%or = or i32 %anda, %shrb
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ret i32 %or
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}
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; ...and again with i64.
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define i64 @f8(i64 %a, i64 %b) {
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; CHECK-LABEL: f8:
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; CHECK: risbg %r2, %r3, 8, 63, 56
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; CHECK: br %r14
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%anda = and i64 %a, -72057594037927936
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%shrb = lshr i64 %b, 8
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%or = or i64 %anda, %shrb
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ret i64 %or
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}
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; Check that we can get the case where a 64-bit shift feeds a 32-bit or of
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; ands with complement masks.
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define signext i32 @f9(i64 %x, i32 signext %y) {
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; CHECK-LABEL: f9:
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; CHECK: risbg [[REG:%r[0-5]]], %r2, 48, 63, 16
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; CHECK: lgfr %r2, [[REG]]
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%shr6 = lshr i64 %x, 48
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%conv = trunc i64 %shr6 to i32
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%and1 = and i32 %y, -65536
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%or = or i32 %conv, %and1
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ret i32 %or
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}
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; Check that we don't get the case where a 64-bit shift feeds a 32-bit or of
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; ands with incompatible masks.
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define signext i32 @f10(i64 %x, i32 signext %y) {
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; CHECK-LABEL: f10:
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; CHECK: nilf %r3, 4278190080
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%shr6 = lshr i64 %x, 48
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%conv = trunc i64 %shr6 to i32
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%and1 = and i32 %y, -16777216
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%or = or i32 %conv, %and1
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ret i32 %or
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}
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