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As a consequence of recent discussions (http://lists.llvm.org/pipermail/llvm-dev/2018-May/123164.html), this patch changes the SystemZ SchedModels so that the IssueWidth is 6, which is the decoder capacity, and NumMicroOps become the number of decoder slots needed per instruction. In addition, the SchedWrite latencies now match the MachineInstructions def-operand indexes, and ReadAdvances have been added on instructions with one register operand and one memory operand. Review: Ulrich Weigand https://reviews.llvm.org/D47008 llvm-svn: 337538
34 lines
1023 B
LLVM
34 lines
1023 B
LLVM
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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;
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; Check that a widening truncate to a vector of i1 elements can be handled.
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define void @pr32275(<4 x i8> %B15) {
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; CHECK-LABEL: pr32275:
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; CHECK: # %bb.0: # %BB
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; CHECK: vlgvb %r0, %v24, 3
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; CHECK-NEXT: vlgvb %r1, %v24, 1
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; CHECK-NEXT: vlvgp [[REG1:%v[0-9]]], %r1, %r0
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; CHECK-NEXT: vlgvb %r0, %v24, 0
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; CHECK-NEXT: vlgvb [[REG3:%r[0-9]]], %v24, 2
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; CHECK-NEXT: vrepif [[REG0:%v[0-9]]], 1
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; CHECK: .LBB0_1:
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; CHECK-DAG: vlr [[REG2:%v[0-9]]], [[REG1]]
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; CHECK-DAG: vlvgf [[REG2]], %r0, 0
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; CHECK-NEXT: vlvgf [[REG2]], [[REG3]], 2
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; CHECK-NEXT: vn [[REG2]], [[REG2]], [[REG0]]
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; CHECK-NEXT: vlgvf [[REG4:%r[0-9]]], [[REG2]], 3
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; CHECK-NEXT: cijlh [[REG4]], 0, .LBB0_1
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; CHECK-NEXT: # %bb.2: # %CF36
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; CHECK-NEXT: br %r14
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BB:
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br label %CF34
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CF34:
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%Tr24 = trunc <4 x i8> %B15 to <4 x i1>
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%E28 = extractelement <4 x i1> %Tr24, i32 3
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br i1 %E28, label %CF34, label %CF36
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CF36:
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ret void
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}
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