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6456c4a101
This is another variation of PR38533. In this case, the result type of the bitcast is legal and 16-bits wide, but not a scalar integer. So we need to emit the convert to i16 and then bitcast it to the true result type. This new bitcast will be further type legalized if necessary. llvm-svn: 339536
66 lines
2.3 KiB
LLVM
66 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX512
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; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch.
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define void @constant_fold_vector_to_half() {
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; CHECK-LABEL: constant_fold_vector_to_half:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000
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; CHECK-NEXT: retq
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store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
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ret void
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}
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; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing.
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define void @pr38533_2(half %x) {
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; SSE-LABEL: pr38533_2:
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; SSE: # %bb.0:
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; SSE-NEXT: pushq %rax
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; SSE-NEXT: .cfi_def_cfa_offset 16
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; SSE-NEXT: callq __gnu_f2h_ieee
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; SSE-NEXT: movw %ax, {{[0-9]+}}(%rsp)
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; SSE-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
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; SSE-NEXT: movw %ax, (%rax)
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; SSE-NEXT: popq %rax
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; SSE-NEXT: .cfi_def_cfa_offset 8
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; SSE-NEXT: retq
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;
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; AVX512-LABEL: pr38533_2:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; AVX512-NEXT: vmovd %xmm0, %eax
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; AVX512-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
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; AVX512-NEXT: movw %ax, (%rax)
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; AVX512-NEXT: retq
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%a = bitcast half %x to <4 x i4>
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store volatile <4 x i4> %a, <4 x i4>* undef
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ret void
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}
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; This case is a bitcast from fp16 to a 16-bit wide legal vector type. In this case the result type is legal when the bitcast gets type legalized.
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define void @pr38533_3(half %x) {
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; SSE-LABEL: pr38533_3:
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; SSE: # %bb.0:
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; SSE-NEXT: pushq %rax
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; SSE-NEXT: .cfi_def_cfa_offset 16
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; SSE-NEXT: callq __gnu_f2h_ieee
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; SSE-NEXT: movw %ax, (%rsp)
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; SSE-NEXT: movzwl (%rsp), %eax
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; SSE-NEXT: movw %ax, (%rax)
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; SSE-NEXT: popq %rax
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; SSE-NEXT: .cfi_def_cfa_offset 8
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; SSE-NEXT: retq
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;
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; AVX512-LABEL: pr38533_3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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; AVX512-NEXT: vmovd %xmm0, %eax
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; AVX512-NEXT: movw %ax, (%rax)
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; AVX512-NEXT: retq
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%a = bitcast half %x to <16 x i1>
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store volatile <16 x i1> %a, <16 x i1>* undef
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ret void
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}
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