mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 20:43:44 +02:00
ec0afdb0d7
The bug has been lying dormant, but apparently was never exposed, until after rL324941 because we didn't return the correct result for shifts with undef operands. llvm-svn: 325010
461 lines
10 KiB
LLVM
461 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i32 @add_undef_rhs(i32 %x) {
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; CHECK-LABEL: add_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = add i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @add_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: add_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = add <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @add_undef_lhs(i32 %x) {
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; CHECK-LABEL: add_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = add i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @add_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: add_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = add <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @sub_undef_rhs(i32 %x) {
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; CHECK-LABEL: sub_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sub i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @sub_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: sub_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sub <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @sub_undef_lhs(i32 %x) {
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; CHECK-LABEL: sub_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sub i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @sub_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: sub_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sub <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @mul_undef_rhs(i32 %x) {
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; CHECK-LABEL: mul_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = mul i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @mul_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: mul_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = mul <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @mul_undef_lhs(i32 %x) {
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; CHECK-LABEL: mul_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = mul i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @mul_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: mul_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = mul <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @sdiv_undef_rhs(i32 %x) {
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; CHECK-LABEL: sdiv_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sdiv i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @sdiv_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: sdiv_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = sdiv <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @sdiv_undef_lhs(i32 %x) {
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; CHECK-LABEL: sdiv_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = sdiv i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @sdiv_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: sdiv_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = sdiv <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @udiv_undef_rhs(i32 %x) {
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; CHECK-LABEL: udiv_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = udiv i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @udiv_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: udiv_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = udiv <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @udiv_undef_lhs(i32 %x) {
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; CHECK-LABEL: udiv_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = udiv i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @udiv_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: udiv_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = udiv <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @srem_undef_rhs(i32 %x) {
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; CHECK-LABEL: srem_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = srem i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @srem_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: srem_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = srem <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @srem_undef_lhs(i32 %x) {
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; CHECK-LABEL: srem_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = srem i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @srem_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: srem_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = srem <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @urem_undef_rhs(i32 %x) {
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; CHECK-LABEL: urem_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = urem i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @urem_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: urem_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = urem <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @urem_undef_lhs(i32 %x) {
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; CHECK-LABEL: urem_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = urem i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @urem_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: urem_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = urem <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @ashr_undef_rhs(i32 %x) {
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; CHECK-LABEL: ashr_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = ashr i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @ashr_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: ashr_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = ashr <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @ashr_undef_lhs(i32 %x) {
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; CHECK-LABEL: ashr_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = ashr i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @ashr_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: ashr_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = ashr <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @lshr_undef_rhs(i32 %x) {
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; CHECK-LABEL: lshr_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = lshr i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @lshr_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: lshr_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = lshr <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @lshr_undef_lhs(i32 %x) {
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; CHECK-LABEL: lshr_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = lshr i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @lshr_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: lshr_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = lshr <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @shl_undef_rhs(i32 %x) {
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; CHECK-LABEL: shl_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = shl i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @shl_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: shl_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = shl <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @shl_undef_lhs(i32 %x) {
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; CHECK-LABEL: shl_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = shl i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @shl_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: shl_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = shl <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @and_undef_rhs(i32 %x) {
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; CHECK-LABEL: and_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = and i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @and_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: and_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = and <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @and_undef_lhs(i32 %x) {
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; CHECK-LABEL: and_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%r = and i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @and_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: and_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = and <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @or_undef_rhs(i32 %x) {
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; CHECK-LABEL: or_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%r = or i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @or_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: or_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = or <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @or_undef_lhs(i32 %x) {
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; CHECK-LABEL: or_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%r = or i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @or_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: or_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: retq
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%r = or <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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define i32 @xor_undef_rhs(i32 %x) {
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; CHECK-LABEL: xor_undef_rhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = xor i32 %x, undef
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ret i32 %r
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}
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define <4 x i32> @xor_undef_rhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: xor_undef_rhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = xor <4 x i32> %x, undef
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ret <4 x i32> %r
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}
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define i32 @xor_undef_lhs(i32 %x) {
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; CHECK-LABEL: xor_undef_lhs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = xor i32 undef, %x
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ret i32 %r
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}
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define <4 x i32> @xor_undef_lhs_vec(<4 x i32> %x) {
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; CHECK-LABEL: xor_undef_lhs_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%r = xor <4 x i32> undef, %x
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ret <4 x i32> %r
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}
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; This would crash because the shift amount is an i8 operand,
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; but the result of the shift is i32. We can't just propagate
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; the existing undef as the result.
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define i1 @undef_operand_size_not_same_as_result() {
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; CHECK-LABEL: undef_operand_size_not_same_as_result:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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%sh = shl i32 7, undef
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%cmp = icmp eq i32 0, %sh
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ret i1 %cmp
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}
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