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4186ef5531
The `sgt/sgtu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is greater than `Src2/Imm` and to 0 otherwise. Differential Revision: https://reviews.llvm.org/D64313 llvm-svn: 365475
25 lines
1.0 KiB
ArmAsm
25 lines
1.0 KiB
ArmAsm
# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
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sgt $4, $5
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# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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sgt $4, $5, $6
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# CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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sgt $4, $5, 16
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# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
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# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
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sgtu $4, $5
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# CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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sgtu $4, $5, $6
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# CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
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sgtu $4, $5, 16
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# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
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# CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
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sgt $4, 16
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# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
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# CHECK: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
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sgtu $4, 16
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# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
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# CHECK: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
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