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llvm-mirror/test
Sanjay Patel fcfe9b03ff [InstCombine] propagate fast-math-flags (FMF) to select when inverting fcmp+select
As noted by the FIXME comment, this is not correct based on our current FMF semantics.
We should be propagating FMF from the final value in a sequence (in this case the
'select'). So the behavior even without this patch is wrong, but we did not allow FMF
on 'select' until recently.

But if we do the correct thing right now in this patch, we'll inevitably introduce
regressions because we have not wired up FMF propagation for 'phi' and 'select' in
other passes (like SimplifyCFG) or other places in InstCombine. I'm not seeing a
better incremental way to make progress.

That said, the potential extra damage over the existing wrong behavior from this
patch is very limited. AFAIK, the only way to have different FMF on IR in the same
function is if we have LTO inlined IR from 2 modules that were compiled using
different fast-math settings.

As seen in the tests, we may actually see some improvements with this patch because
adding the FMF to the 'select' allows matching to min/max intrinsics that were
previously missed (in the common case, the 'fcmp' and 'select' should have identical
FMF to begin with).

Next steps in the transition:

    Make similar changes in instcombine as needed.
    Enable phi-to-select FMF propagation in SimplifyCFG.
    Remove dependencies on fcmp with FMF.
    Deprecate FMF on fcmp.

Differential Revision: https://reviews.llvm.org/D69720
2019-11-13 10:38:42 -05:00
..
Analysis Remove commented out CHECK-NEXT to try and appease llvm-clang-x86_64-expensive-checks-win buildbot 2019-11-13 14:59:12 +00:00
Assembler ThinLTO : Import always_inline functions irrespective of the threshold 2019-11-08 17:02:01 -08:00
Bindings [IR] Redefine Freeze instruction 2019-11-12 10:49:00 +09:00
Bitcode [IR] Redefine Freeze instruction 2019-11-12 10:49:00 +09:00
BugPoint
CodeGen Revert "[RISCV] Fix wrong CFI directives" 2019-11-13 13:28:33 +00:00
DebugInfo [DebugInfo] Avoid creating entry values for clobbered registers 2019-11-13 11:10:47 +01:00
Demangle
Examples [Examples] Add IRTransformations directory to examples. 2019-11-12 14:14:48 +00:00
ExecutionEngine [JITLink] Refactor EH-frame handling to support eh-frames with existing relocs. 2019-11-06 14:30:26 -08:00
Feature [SLP] allow forming 2-way reduction patterns 2019-11-07 06:08:42 -05:00
FileCheck
Instrumentation
Integer
JitListener
Linker [IRMover] Set Address Space for moved global values 2019-11-05 16:32:48 -08:00
LTO
MachineVerifier Revert "[MachineVerifier] Improve verification of live-in lists. 2019-11-07 14:02:13 -08:00
MC ARM: Don't emit R_ARM_NONE relocations to compact unwinding decoders in .ARM.exidx on Android. 2019-11-12 10:52:59 -08:00
Object [Object][MachO] Rewrite macho-invalid-fat-arch-size into YAML 2019-11-06 11:26:25 -08:00
ObjectYAML
Other
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86 ThinLTO : Import always_inline functions irrespective of the threshold 2019-11-08 17:02:01 -08:00
tools [llvm-objcopy][COFF] Implement --redefine-sym and --redefine-syms 2019-11-12 11:28:00 -08:00
Transforms [InstCombine] propagate fast-math-flags (FMF) to select when inverting fcmp+select 2019-11-13 10:38:42 -05:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh