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22e87bbb08
Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
132 lines
4.3 KiB
C++
132 lines
4.3 KiB
C++
//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
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#include "ARMInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class ARMBaseTargetMachine : public LLVMTargetMachine {
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public:
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enum ARMABI {
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ARM_ABI_UNKNOWN,
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ARM_ABI_APCS,
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ARM_ABI_AAPCS, // ARM EABI
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ARM_ABI_AAPCS16
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} TargetABI;
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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ARMSubtarget Subtarget;
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bool isLittle;
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mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
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public:
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ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle);
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~ARMBaseTargetMachine() override;
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const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
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const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
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bool isLittleEndian() const { return isLittle; }
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/// \brief Get the TargetIRAnalysis for this target.
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TargetIRAnalysis getTargetIRAnalysis() override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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};
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/// ARM target machine.
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///
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class ARMTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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public:
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ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle);
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};
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/// ARM little endian target machine.
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///
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class ARMLETargetMachine : public ARMTargetMachine {
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void anchor() override;
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public:
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ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// ARM big endian target machine.
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///
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class ARMBETargetMachine : public ARMTargetMachine {
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void anchor() override;
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public:
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ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// Thumb target machine.
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/// Due to the way architectures are handled, this represents both
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/// Thumb-1 and Thumb-2.
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///
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class ThumbTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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public:
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ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL, bool isLittle);
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};
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/// Thumb little endian target machine.
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///
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class ThumbLETargetMachine : public ThumbTargetMachine {
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void anchor() override;
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public:
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ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// Thumb big endian target machine.
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///
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class ThumbBETargetMachine : public ThumbTargetMachine {
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void anchor() override;
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public:
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ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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