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86fa0255b2
The way the named arguments for various system instructions are handled at the
moment has a few problems:
- Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
- That weird Mapping class that I have no idea what I was on when I thought
it was a good idea.
- Searches are performed linearly through the entire list.
- We print absolutely all registers in upper-case, even though some are
canonically mixed case (SPSel for example).
- The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
to comments in our implementation, with a slightly opaque hex value
indicating the canonical encoding LLVM will use.
This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.
llvm-svn: 274576
75 lines
2.3 KiB
CMake
75 lines
2.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AArch64.td)
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tablegen(LLVM AArch64GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
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tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)
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add_public_tablegen_target(AArch64CommonTableGen)
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# List of all GlobalISel files.
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set(GLOBAL_ISEL_FILES
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AArch64CallLowering.cpp
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AArch64RegisterBankInfo.cpp
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)
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# Add GlobalISel files to the dependencies if the user wants to build it.
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if(LLVM_BUILD_GLOBAL_ISEL)
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set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
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else()
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set(GLOBAL_ISEL_BUILD_FILES"")
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set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
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endif()
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add_llvm_target(AArch64CodeGen
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AArch64A57FPLoadBalancing.cpp
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AArch64AddressTypePromotion.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
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AArch64BranchRelaxation.cpp
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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AArch64ConditionalCompares.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandPseudoInsts.cpp
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AArch64FastISel.cpp
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AArch64A53Fix835769.cpp
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AArch64FrameLowering.cpp
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AArch64ConditionOptimizer.cpp
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AArch64RedundantCopyElimination.cpp
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AArch64ISelDAGToDAG.cpp
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AArch64ISelLowering.cpp
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AArch64InstrInfo.cpp
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AArch64LoadStoreOptimizer.cpp
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AArch64MCInstLower.cpp
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AArch64PromoteConstant.cpp
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AArch64PBQPRegAlloc.cpp
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AArch64RegisterInfo.cpp
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AArch64SelectionDAGInfo.cpp
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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AArch64TargetMachine.cpp
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AArch64TargetObjectFile.cpp
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AArch64TargetTransformInfo.cpp
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${GLOBAL_ISEL_BUILD_FILES}
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)
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add_dependencies(LLVMAArch64CodeGen intrinsics_gen)
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add_subdirectory(TargetInfo)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Utils)
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