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262 lines
8.9 KiB
C++
262 lines
8.9 KiB
C++
//===-- LanaiDelaySlotFiller.cpp - Lanai delay slot filler ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Simple pass to fill delay slots with useful instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "Lanai.h"
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#include "LanaiTargetMachine.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "delay-slot-filler"
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STATISTIC(FilledSlots, "Number of delay slots filled");
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static cl::opt<bool>
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NopDelaySlotFiller("lanai-nop-delay-filler", cl::init(false),
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cl::desc("Fill Lanai delay slots with NOPs."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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// Target machine description which we query for reg. names, data
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// layout, etc.
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineBasicBlock::instr_iterator LastFiller;
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static char ID;
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explicit Filler() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "Lanai Delay Slot Filler"; }
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &MF) override {
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const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>();
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TII = Subtarget.getInstrInfo();
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TRI = Subtarget.getRegisterInfo();
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bool Changed = false;
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for (MachineFunction::iterator FI = MF.begin(), FE = MF.end(); FI != FE;
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++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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void insertDefsUses(MachineBasicBlock::instr_iterator MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
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bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
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bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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bool findDelayInstr(MachineBasicBlock &MBB,
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MachineBasicBlock::instr_iterator Slot,
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MachineBasicBlock::instr_iterator &Filler);
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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// createLanaiDelaySlotFillerPass - Returns a pass that fills in delay
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// slots in Lanai MachineFunctions
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FunctionPass *
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llvm::createLanaiDelaySlotFillerPass(const LanaiTargetMachine & /*tm*/) {
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return new Filler();
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}
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// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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// There is one or two delay slot per delayed instruction.
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bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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LastFiller = MBB.instr_end();
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for (MachineBasicBlock::instr_iterator I = MBB.instr_begin();
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I != MBB.instr_end(); ++I) {
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if (I->getDesc().hasDelaySlot()) {
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MachineBasicBlock::instr_iterator InstrWithSlot = I;
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MachineBasicBlock::instr_iterator J = I;
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// Treat RET specially as it is only instruction with 2 delay slots
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// generated while all others generated have 1 delay slot.
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if (I->getOpcode() == Lanai::RET) {
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// RET is generated as part of epilogue generation and hence we know
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// what the two instructions preceding it are and that it is safe to
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// insert RET above them.
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MachineBasicBlock::reverse_instr_iterator RI = ++I.getReverse();
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assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
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RI->getOperand(0).getReg() == Lanai::FP &&
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RI->getOperand(1).isReg() &&
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RI->getOperand(1).getReg() == Lanai::FP &&
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RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8);
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++RI;
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assert(RI->getOpcode() == Lanai::ADD_I_LO &&
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RI->getOperand(0).isReg() &&
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RI->getOperand(0).getReg() == Lanai::SP &&
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RI->getOperand(1).isReg() &&
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RI->getOperand(1).getReg() == Lanai::FP);
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MachineBasicBlock::instr_iterator FI = RI.getReverse();
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MBB.splice(std::next(I), &MBB, FI, I);
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FilledSlots += 2;
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} else {
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if (!NopDelaySlotFiller && findDelayInstr(MBB, I, J)) {
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MBB.splice(std::next(I), &MBB, J);
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} else {
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BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP));
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}
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++FilledSlots;
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}
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Changed = true;
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// Record the filler instruction that filled the delay slot.
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// The instruction after it will be visited in the next iteration.
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LastFiller = ++I;
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// Bundle the delay slot filler to InstrWithSlot so that the machine
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// verifier doesn't expect this instruction to be a terminator.
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MIBundleBuilder(MBB, InstrWithSlot, std::next(LastFiller));
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}
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}
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return Changed;
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}
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bool Filler::findDelayInstr(MachineBasicBlock &MBB,
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MachineBasicBlock::instr_iterator Slot,
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MachineBasicBlock::instr_iterator &Filler) {
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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insertDefsUses(Slot, RegDefs, RegUses);
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bool SawLoad = false;
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bool SawStore = false;
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for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
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I != MBB.instr_rend(); ++I) {
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// skip debug value
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if (I->isDebugInstr())
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continue;
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// Convert to forward iterator.
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MachineBasicBlock::instr_iterator FI = I.getReverse();
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if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isLabel() ||
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FI == LastFiller || I->isPseudo())
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break;
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if (delayHasHazard(FI, SawLoad, SawStore, RegDefs, RegUses)) {
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insertDefsUses(FI, RegDefs, RegUses);
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continue;
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}
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Filler = FI;
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return true;
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}
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return false;
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}
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bool Filler::delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
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bool &SawStore, SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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if (MI->isImplicitDef() || MI->isKill())
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return true;
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// Loads or stores cannot be moved past a store to the delay slot
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// and stores cannot be moved past a load.
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if (MI->mayLoad()) {
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if (SawStore)
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return true;
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SawLoad = true;
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}
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if (MI->mayStore()) {
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if (SawStore)
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return true;
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SawStore = true;
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if (SawLoad)
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return true;
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}
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assert((!MI->isCall() && !MI->isReturn()) &&
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"Cannot put calls or returns in delay slot.");
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI->getOperand(I);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue; // skip
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if (MO.isDef()) {
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// check whether Reg is defined or used before delay slot.
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if (isRegInSet(RegDefs, Reg) || isRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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// check whether Reg is defined before delay slot.
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if (isRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(MachineBasicBlock::instr_iterator MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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// If MI is a call or return, just examine the explicit non-variadic operands.
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MCInstrDesc MCID = MI->getDesc();
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unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands()
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: MI->getNumOperands();
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for (unsigned I = 0; I != E; ++I) {
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const MachineOperand &MO = MI->getOperand(I);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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}
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// Call & return instructions defines SP implicitly. Implicit defines are not
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// included in the RegDefs set of calls but instructions modifying SP cannot
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// be inserted in the delay slot of a call/return as these instructions are
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// expanded to multiple instructions with SP modified before the branch that
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// has the delay slot.
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if (MI->isCall() || MI->isReturn())
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RegDefs.insert(Lanai::SP);
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}
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// Returns true if the Reg or its alias is in the RegSet.
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bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
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// Check Reg and all aliased Registers.
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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if (RegSet.count(*AI))
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return true;
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return false;
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}
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