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llvm-mirror/test/TableGen/condsbit.td
Paul C. Anagnostopoulos 0830936d52 [TableGen] Add true and false literals to represent booleans
Update the Programmer's Reference document.

Add a test. Update a couple of tests with an improved error message.

Differential Revision: https://reviews.llvm.org/D90635
2020-11-05 09:07:21 -05:00

24 lines
434 B
TableGen

// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// Check that !cond works well with bit conditional values.
class A<bit b = true> {
int a = !cond(b: 5, true : 6);
bit c = !cond(b: false, true : true);
bits<1> d = !cond(b: 0, true : 1);
}
// CHECK: def X
// CHECK: a = 6
// CHECK: c = 1
// CHECK: d = { 1 }
// CHECK: def Y
// CHECK: a = 5
// CHECK: c = 0
// CHECK: d = { 0 }
def X : A<false>;
def Y : A;