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9cc166efe6
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
104 lines
3.0 KiB
C++
104 lines
3.0 KiB
C++
//===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the assembly expression modifiers
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// accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVMCExpr.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscvmcexpr"
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const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind,
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MCContext &Ctx) {
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return new (Ctx) RISCVMCExpr(Expr, Kind);
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}
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void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
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bool HasVariant = getKind() != VK_RISCV_None;
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if (HasVariant)
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OS << '%' << getVariantKindName(getKind()) << '(';
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Expr->print(OS, MAI);
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if (HasVariant)
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OS << ')';
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}
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bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
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const MCAsmLayout *Layout,
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const MCFixup *Fixup) const {
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return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);
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}
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void RISCVMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
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Streamer.visitUsedExpr(*getSubExpr());
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}
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RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) {
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return StringSwitch<RISCVMCExpr::VariantKind>(name)
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.Case("lo", VK_RISCV_LO)
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.Case("hi", VK_RISCV_HI)
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.Case("pcrel_lo", VK_RISCV_PCREL_LO)
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.Case("pcrel_hi", VK_RISCV_PCREL_HI)
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.Default(VK_RISCV_Invalid);
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}
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StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Invalid ELF symbol kind");
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case VK_RISCV_LO:
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return "lo";
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case VK_RISCV_HI:
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return "hi";
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case VK_RISCV_PCREL_LO:
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return "pcrel_lo";
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case VK_RISCV_PCREL_HI:
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return "pcrel_hi";
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}
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}
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bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
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MCValue Value;
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if (Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO)
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return false;
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if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr))
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return false;
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if (!Value.isAbsolute())
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return false;
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Res = evaluateAsInt64(Value.getConstant());
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return true;
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}
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int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const {
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switch (Kind) {
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default:
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llvm_unreachable("Invalid kind");
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case VK_RISCV_LO:
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return SignExtend64<12>(Value);
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case VK_RISCV_HI:
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// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
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return ((Value + 0x800) >> 12) & 0xfffff;
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}
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}
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