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https://github.com/RPCS3/llvm-mirror.git
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f891b70313
This commit serializes the fixed stack objects, including fixed spill slots. The fixed stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset, and alignment. The objects that aren't spill slots also serialize the isImmutable and isAliased flags. The fixed stack objects are a part of the machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242045
341 lines
11 KiB
C++
341 lines
11 KiB
C++
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the class that prints out the LLVM IR and machine
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// functions using the MIR serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "MIRPrinter.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/YAMLTraits.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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/// This class prints out the machine functions using the MIR serialization
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/// format.
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class MIRPrinter {
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raw_ostream &OS;
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DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
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public:
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MIRPrinter(raw_ostream &OS) : OS(OS) {}
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
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void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB);
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void convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI);
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private:
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void initRegisterMaskIds(const MachineFunction &MF);
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};
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/// This class prints out the machine instructions using the MIR serialization
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/// format.
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class MIPrinter {
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raw_ostream &OS;
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ModuleSlotTracker &MST;
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
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public:
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MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds)
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: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds) {}
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void print(const MachineInstr &MI);
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void printMBBReference(const MachineBasicBlock &MBB);
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void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
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};
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} // end anonymous namespace
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namespace llvm {
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namespace yaml {
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/// This struct serializes the LLVM IR module.
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template <> struct BlockScalarTraits<Module> {
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static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
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Mod.print(OS, nullptr);
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}
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static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
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llvm_unreachable("LLVM Module is supposed to be parsed separately");
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return "";
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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void MIRPrinter::print(const MachineFunction &MF) {
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initRegisterMaskIds(MF);
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yaml::MachineFunction YamlMF;
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YamlMF.Name = MF.getName();
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YamlMF.Alignment = MF.getAlignment();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.HasInlineAsm = MF.hasInlineAsm();
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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convert(YamlMF.FrameInfo, *MF.getFrameInfo());
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convertStackObjects(YamlMF, *MF.getFrameInfo());
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int I = 0;
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ModuleSlotTracker MST(MF.getFunction()->getParent());
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for (const auto &MBB : MF) {
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// TODO: Allow printing of non sequentially numbered MBBs.
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// This is currently needed as the basic block references get their index
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// from MBB.getNumber(), thus it should be sequential so that the parser can
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// map back to the correct MBBs when parsing the output.
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assert(MBB.getNumber() == I++ &&
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"Can't print MBBs that aren't sequentially numbered");
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(void)I;
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yaml::MachineBasicBlock YamlMBB;
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convert(MST, YamlMBB, MBB);
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YamlMF.BasicBlocks.push_back(YamlMBB);
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}
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yaml::Output Out(OS);
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Out << YamlMF;
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.IsSSA = RegInfo.isSSA();
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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VReg.Class =
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StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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MF.VirtualRegisters.push_back(VReg);
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}
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}
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void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI) {
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YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
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YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
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YamlMFI.HasStackMap = MFI.hasStackMap();
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YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
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YamlMFI.StackSize = MFI.getStackSize();
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YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
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YamlMFI.MaxAlignment = MFI.getMaxAlignment();
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YamlMFI.AdjustsStack = MFI.adjustsStack();
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YamlMFI.HasCalls = MFI.hasCalls();
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YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
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YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
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YamlMFI.HasVAStart = MFI.hasVAStart();
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YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
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}
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void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI) {
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// Process fixed stack objects.
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unsigned ID = 0;
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for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::FixedMachineStackObject YamlObject;
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YamlObject.ID = ID++;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::FixedMachineStackObject::SpillSlot
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: yaml::FixedMachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
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YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
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MF.FixedStackObjects.push_back(YamlObject);
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// TODO: Store the mapping between fixed object IDs and object indices to
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// print the fixed stack object references correctly.
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}
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// Process ordinary stack objects.
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ID = 0;
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for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::MachineStackObject YamlObject;
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YamlObject.ID = ID++;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::MachineStackObject::SpillSlot
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: yaml::MachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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MF.StackObjects.push_back(YamlObject);
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// TODO: Store the mapping between object IDs and object indices to print
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// the stack object references correctly.
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB) {
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assert(MBB.getNumber() >= 0 && "Invalid MBB number");
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YamlMBB.ID = (unsigned)MBB.getNumber();
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// TODO: Serialize unnamed BB references.
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if (const auto *BB = MBB.getBasicBlock())
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YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
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else
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YamlMBB.Name.Value = "";
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YamlMBB.Alignment = MBB.getAlignment();
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YamlMBB.AddressTaken = MBB.hasAddressTaken();
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YamlMBB.IsLandingPad = MBB.isLandingPad();
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for (const auto *SuccMBB : MBB.successors()) {
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std::string Str;
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds).printMBBReference(*SuccMBB);
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YamlMBB.Successors.push_back(StrOS.str());
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}
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// Print the machine instructions.
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YamlMBB.Instructions.reserve(MBB.size());
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std::string Str;
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for (const auto &MI : MBB) {
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds).print(MI);
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YamlMBB.Instructions.push_back(StrOS.str());
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Str.clear();
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}
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}
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void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
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const auto *TRI = MF.getSubtarget().getRegisterInfo();
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unsigned I = 0;
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for (const uint32_t *Mask : TRI->getRegMasks())
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RegisterMaskIds.insert(std::make_pair(Mask, I++));
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}
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void MIPrinter::print(const MachineInstr &MI) {
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const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
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const auto *TRI = SubTarget.getRegisterInfo();
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assert(TRI && "Expected target register info");
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const auto *TII = SubTarget.getInstrInfo();
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assert(TII && "Expected target instruction info");
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unsigned I = 0, E = MI.getNumOperands();
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for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
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!MI.getOperand(I).isImplicit();
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++I) {
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if (I)
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OS << ", ";
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print(MI.getOperand(I), TRI);
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}
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if (I)
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OS << " = ";
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OS << TII->getName(MI.getOpcode());
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// TODO: Print the instruction flags, machine mem operands.
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if (I < E)
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OS << ' ';
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bool NeedComma = false;
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for (; I < E; ++I) {
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if (NeedComma)
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OS << ", ";
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print(MI.getOperand(I), TRI);
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NeedComma = true;
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}
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}
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static void printReg(unsigned Reg, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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// TODO: Print Stack Slots.
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if (!Reg)
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OS << '_';
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
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else if (Reg < TRI->getNumRegs())
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OS << '%' << StringRef(TRI->getName(Reg)).lower();
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else
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llvm_unreachable("Can't print this kind of register yet");
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}
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void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
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OS << "%bb." << MBB.getNumber();
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if (const auto *BB = MBB.getBasicBlock()) {
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if (BB->hasName())
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OS << '.' << BB->getName();
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}
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}
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void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
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switch (Op.getType()) {
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case MachineOperand::MO_Register:
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// TODO: Print the other register flags.
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if (Op.isImplicit())
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OS << (Op.isDef() ? "implicit-def " : "implicit ");
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if (Op.isDead())
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OS << "dead ";
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if (Op.isKill())
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OS << "killed ";
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if (Op.isUndef())
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OS << "undef ";
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printReg(Op.getReg(), OS, TRI);
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// TODO: Print sub register.
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break;
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case MachineOperand::MO_Immediate:
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OS << Op.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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printMBBReference(*Op.getMBB());
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break;
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case MachineOperand::MO_GlobalAddress:
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Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
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// TODO: Print offset and target flags.
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break;
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case MachineOperand::MO_RegisterMask: {
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auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
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if (RegMaskInfo != RegisterMaskIds.end())
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OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
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else
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llvm_unreachable("Can't print this machine register mask yet.");
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break;
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}
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default:
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// TODO: Print the other machine operands.
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llvm_unreachable("Can't print this machine operand at the moment");
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}
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}
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void llvm::printMIR(raw_ostream &OS, const Module &M) {
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yaml::Output Out(OS);
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Out << const_cast<Module &>(M);
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}
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void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
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MIRPrinter Printer(OS);
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Printer.print(MF);
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}
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