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Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
97 lines
2.3 KiB
LLVM
97 lines
2.3 KiB
LLVM
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s
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define i32 @TestComp128GT(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp ogt fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128GT:
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; CHECK: callq __gttf2
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; CHECK: setg %al
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; CHECK: movzbl %al, %eax
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; CHECK: retq
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}
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define i32 @TestComp128GE(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp oge fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128GE:
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; CHECK: callq __getf2
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; CHECK: testl %eax, %eax
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; CHECK: setns %al
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; CHECK: movzbl %al, %eax
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; CHECK: retq
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}
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define i32 @TestComp128LT(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp olt fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128LT:
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; CHECK: callq __lttf2
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; CHECK-NEXT: shrl $31, %eax
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; CHECK: retq
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;
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; The 'shrl' is a special optimization in llvm to combine
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; the effect of 'fcmp olt' and 'zext'. The main purpose is
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; to test soften call to __lttf2.
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}
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define i32 @TestComp128LE(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp ole fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128LE:
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; CHECK: callq __letf2
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; CHECK-NEXT: testl %eax, %eax
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; CHECK: setle %al
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; CHECK: movzbl %al, %eax
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; CHECK: retq
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}
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define i32 @TestComp128EQ(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp oeq fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128EQ:
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; CHECK: callq __eqtf2
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; CHECK-NEXT: testl %eax, %eax
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; CHECK: sete %al
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; CHECK: movzbl %al, %eax
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; CHECK: retq
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}
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define i32 @TestComp128NE(fp128 %d1, fp128 %d2) {
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entry:
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%cmp = fcmp une fp128 %d1, %d2
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: TestComp128NE:
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; CHECK: callq __netf2
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; CHECK-NEXT: testl %eax, %eax
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; CHECK: setne %al
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; CHECK: movzbl %al, %eax
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; CHECK: retq
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}
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define fp128 @TestMax(fp128 %x, fp128 %y) {
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entry:
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%cmp = fcmp ogt fp128 %x, %y
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%cond = select i1 %cmp, fp128 %x, fp128 %y
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ret fp128 %cond
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; CHECK-LABEL: TestMax:
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; CHECK: movaps %xmm1
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; CHECK: movaps %xmm0
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; CHECK: callq __gttf2
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; CHECK: movaps {{.*}}, %xmm0
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; CHECK: testl %eax, %eax
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; CHECK: movaps {{.*}}, %xmm0
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; CHECK: retq
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}
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