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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
llvm-mirror/test/CodeGen
Chris Lattner f8f4d3c30a while we're at it, handle 'sdiv exact' of a power of 2 also,
this fixes a few rejects on c++ iterator loops.

llvm-svn: 129694
2011-04-18 07:00:40 +00:00
..
Alpha
ARM Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand the node to a libcall. rdar://9280991 2011-04-16 03:08:26 +00:00
Blackfin Don't completely eliminate identity copies that also modify super register liveness. 2011-03-31 17:55:25 +00:00
CBackend
CellSPU don't test for codegen of 'store undef' 2011-04-09 02:31:26 +00:00
CPP
Generic Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could 2011-04-09 07:05:44 +00:00
MBlaze Add scheduling information for the MBlaze backend. 2011-04-11 22:31:52 +00:00
Mips Re-enable test o32_cc_vararg.ll. 2011-04-15 22:23:09 +00:00
MSP430 Enhance ComputeMaskedBits to know that aligned frameindexes 2011-02-13 22:25:43 +00:00
PowerPC These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05 21:40:41 +00:00
PTX ptx: support setp's 4-operand format 2011-04-02 08:51:39 +00:00
SPARC These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05 21:40:41 +00:00
SystemZ Fix SystemZ tests 2011-03-31 23:02:12 +00:00
Thumb Follow up on r127913. Fix Thumb revsh isel. rdar://9286766 2011-04-14 23:27:44 +00:00
Thumb2 Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. 2011-04-13 00:38:32 +00:00
X86 while we're at it, handle 'sdiv exact' of a power of 2 also, 2011-04-18 07:00:40 +00:00
XCore Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 2011-03-31 18:42:43 +00:00