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4e2def1840
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
60 lines
1.8 KiB
LLVM
60 lines
1.8 KiB
LLVM
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
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%1 = and i8 %0, 1
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%tobool3 = icmp ne i8 %1, 0
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ret i1 %tobool3
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; CHECK-LABEL: @testi1
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
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entry:
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%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
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ret i32 %0
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; The ABI sign_extend should combine with the any_extend from the asm result,
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; and the result will be 0 or -1. This highlights the fact that only the first
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; bit is meaningful.
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; CHECK-LABEL: @testi32
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], -1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
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ret i8 %0
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; CHECK-LABEL: @testi8
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: li [[REG1:[0-9]+]], 0
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; CHECK-DAG: crmove [[REG2:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
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; CHECK-DAG: li [[REG4:[0-9]+]], 1
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; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
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; CHECK: blr
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}
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attributes #0 = { nounwind }
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