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f91cfcdaed
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the 64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with explicit register names, on PPC64 when an i64 MVT has been requested, we need to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent) registers. At some point, we'll probably want to arrange things so that the generic code in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order to match these inline asm register constraints. If we do that, this change can be reverted. llvm-svn: 187693
66 lines
2.4 KiB
LLVM
66 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-bgq-linux"
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%struct.BG_CoordinateMapping_t = type { [4 x i8] }
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; Function Attrs: alwaysinline inlinehint nounwind
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define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 {
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entry:
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%mapsize.addr = alloca i64, align 8
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%map.addr = alloca %struct.BG_CoordinateMapping_t*, align 8
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%numentries.addr = alloca i64*, align 8
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%r0 = alloca i64, align 8
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%r3 = alloca i64, align 8
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%r4 = alloca i64, align 8
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%r5 = alloca i64, align 8
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%tmp = alloca i64, align 8
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store i64 %mapsize, i64* %mapsize.addr, align 8
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store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8
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store i64* %numentries, i64** %numentries.addr, align 8
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store i64 1055, i64* %r0, align 8
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%0 = load i64* %mapsize.addr, align 8
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store i64 %0, i64* %r3, align 8
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%1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8
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%2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64
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store i64 %2, i64* %r4, align 8
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%3 = load i64** %numentries.addr, align 8
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%4 = ptrtoint i64* %3 to i64
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store i64 %4, i64* %r5, align 8
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%5 = load i64* %r0, align 8
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%6 = load i64* %r3, align 8
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%7 = load i64* %r4, align 8
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%8 = load i64* %r5, align 8
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%9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0
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; CHECK-LABEL: @Kernel_RanksToCoords
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; These need to be 64-bit loads, not 32-bit loads (not lwz).
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; CHECK-NOT: lwz
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; CHECK: #APP
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; CHECK: sc
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; CHECK: #NO_APP
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; CHECK: blr
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%asmresult = extractvalue { i64, i64, i64, i64 } %9, 0
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%asmresult1 = extractvalue { i64, i64, i64, i64 } %9, 1
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%asmresult2 = extractvalue { i64, i64, i64, i64 } %9, 2
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%asmresult3 = extractvalue { i64, i64, i64, i64 } %9, 3
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store i64 %asmresult, i64* %r0, align 8
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store i64 %asmresult1, i64* %r3, align 8
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store i64 %asmresult2, i64* %r4, align 8
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store i64 %asmresult3, i64* %r5, align 8
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%10 = load i64* %r3, align 8
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store i64 %10, i64* %tmp
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%11 = load i64* %tmp
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%conv = trunc i64 %11 to i32
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ret i32 %conv
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}
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attributes #0 = { alwaysinline inlinehint nounwind }
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attributes #1 = { nounwind }
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!0 = metadata !{i32 -2146895770}
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