llvm-mirror

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History

Matt Arsenault e25266fd34 AMDGPU: Partially fix disassembly of MIMG instructions

Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.

The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.

Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.

llvm-svn: 320614

2017-12-13 21:07:51 +00:00

Analysis

[JumpThreading] Preservation of DT and LVI across the pass

2017-12-13 20:52:26 +00:00

Assembler

[ConstantFold] Support vector index when factoring out GEP index into preceding dimensions

2017-12-04 19:56:33 +00:00

Bindings

…

Bitcode

Hardware-assisted AddressSanitizer (llvm part).

2017-12-09 00:21:41 +00:00