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3203edf16f
Improve/implement these methods to improve DAG combining. This mainly concerns intrinsics. Some constant operands to SystemZISD nodes have been marked Opaque to avoid transforming back and forth between generic and target nodes infinitely. Review: Ulrich Weigand llvm-svn: 327765
98 lines
2.9 KiB
LLVM
98 lines
2.9 KiB
LLVM
; Test that DAGCombiner gets helped by ComputeNumSignBitsForTargetNode() with
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; vector intrinsics.
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;
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; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 < %s | FileCheck %s
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declare <8 x i16> @llvm.s390.vuphb(<16 x i8>)
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; VUPHB
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define <8 x i16> @f0() {
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; CHECK-LABEL: f0:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuphb %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <8 x i16> @llvm.s390.vuphb(<16 x i8>
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<i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1,
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i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1>)
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%trunc = trunc <8 x i16> %unp to <8 x i8>
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%ret = sext <8 x i8> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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declare <4 x i32> @llvm.s390.vuphh(<8 x i16>)
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; VUPHH
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define <4 x i32> @f1() {
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; CHECK-LABEL: f1:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuphh %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <4 x i32> @llvm.s390.vuphh(<8 x i16>
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<i16 0, i16 1, i16 0, i16 1,
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i16 0, i16 1, i16 0, i16 1>)
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%trunc = trunc <4 x i32> %unp to <4 x i16>
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%ret = sext <4 x i16> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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declare <2 x i64> @llvm.s390.vuphf(<4 x i32>)
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; VUPHF
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define <2 x i64> @f2() {
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; CHECK-LABEL: f2:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuphf %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <2 x i64> @llvm.s390.vuphf(<4 x i32> <i32 0, i32 1, i32 0, i32 1>)
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%trunc = trunc <2 x i64> %unp to <2 x i32>
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%ret = sext <2 x i32> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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declare <8 x i16> @llvm.s390.vuplb(<16 x i8>)
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; VUPLB
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define <8 x i16> @f3() {
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; CHECK-LABEL: f3:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuplb %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <8 x i16> @llvm.s390.vuplb(<16 x i8>
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<i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1,
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i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1>)
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%trunc = trunc <8 x i16> %unp to <8 x i8>
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%ret = sext <8 x i8> %trunc to <8 x i16>
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ret <8 x i16> %ret
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}
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declare <4 x i32> @llvm.s390.vuplhw(<8 x i16>)
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; VUPLHW
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define <4 x i32> @f4() {
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; CHECK-LABEL: f4:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuplhw %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <4 x i32> @llvm.s390.vuplhw(<8 x i16>
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<i16 1, i16 0, i16 1, i16 0,
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i16 1, i16 0, i16 1, i16 0>)
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%trunc = trunc <4 x i32> %unp to <4 x i16>
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%ret = sext <4 x i16> %trunc to <4 x i32>
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ret <4 x i32> %ret
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}
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declare <2 x i64> @llvm.s390.vuplf(<4 x i32>)
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; VUPLF
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define <2 x i64> @f5() {
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; CHECK-LABEL: f5:
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; CHECK-LABEL: # %bb.0:
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; CHECK: vuplf %v24, %v0
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; CHECK-NEXT: br %r14
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%unp = call <2 x i64> @llvm.s390.vuplf(<4 x i32> <i32 1, i32 0, i32 1, i32 0>)
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%trunc = trunc <2 x i64> %unp to <2 x i32>
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%ret = sext <2 x i32> %trunc to <2 x i64>
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ret <2 x i64> %ret
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}
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