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50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @fsub_f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W
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; SI-CHECK: @fsub_f32
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; SI-CHECK: V_SUB_F32
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define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fsub float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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; R600-CHECK: @fsub_v2f32
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; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
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; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
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; SI-CHECK: @fsub_v2f32
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; SI-CHECK: V_SUB_F32
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; SI-CHECK: V_SUB_F32
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define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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entry:
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%0 = fsub <2 x float> %a, %b
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @fsub_v4f32
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
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; SI-CHECK: @fsub_v4f32
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; SI-CHECK: V_SUB_F32
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; SI-CHECK: V_SUB_F32
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; SI-CHECK: V_SUB_F32
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; SI-CHECK: V_SUB_F32
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define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fsub <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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ret void
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}
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