..
AsmParser
[RISCV] Improve VMConstraint checking on more unary and nullary instructions.
2020-12-26 18:47:59 -08:00
Disassembler
MCTargetDesc
[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output
2020-12-14 10:50:26 -08:00
TargetInfo
Utils
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source
2020-12-29 10:37:58 -08:00
CMakeLists.txt
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCV.h
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCV.td
[RISCV] V does not imply F.
2020-12-17 10:57:36 +08:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp
[RISCV] Define vmclr.m/vmset.m intrinsics.
2020-12-28 18:57:17 -08:00
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td
[RISCV] Improve VMConstraint checking on more unary and nullary instructions.
2020-12-26 18:47:59 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp
[Target] Use llvm::erase_if (NFC)
2020-12-20 17:43:22 -08:00
RISCVInstrInfo.h
RISCVInstrInfo.td
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
2020-12-10 19:25:51 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td
[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions
2020-12-10 19:25:51 +00:00
RISCVInstrInfoC.td
[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
2020-12-04 10:34:12 -08:00
RISCVInstrInfoD.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
[RISCV] Improve VMConstraint checking on more unary and nullary instructions.
2020-12-26 18:47:59 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source
2020-12-29 10:37:58 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Fill out basic integer RVV ISel patterns
2020-12-29 19:32:18 +00:00
RISCVInstrInfoZfh.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp
[RISCV] Pattern-match more vector-splatted constants
2020-12-28 07:11:10 +00:00
RISCVISelDAGToDAG.h
[RISCV] Add ISel support for RVV vector/scalar forms
2020-12-23 20:16:18 +00:00
RISCVISelLowering.cpp
[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source
2020-12-29 10:37:58 -08:00
RISCVISelLowering.h
[RISCV] Add ISel support for RVV vector/scalar forms
2020-12-23 20:16:18 +00:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp
[RISCV] Basic jump table lowering
2020-12-22 15:05:54 +00:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td
[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
2020-12-20 22:57:07 -08:00
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h
