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llvm-mirror/test/CodeGen/PowerPC/ifcvt.ll
Hal Finkel b556d850c9 Enable early if conversion on PPC
On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.

Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.

llvm-svn: 178926
2013-04-05 23:29:01 +00:00

35 lines
1.2 KiB
LLVM

; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
entry:
%sext82 = shl i32 %d, 16
%conv29 = ashr exact i32 %sext82, 16
%cmp = icmp slt i32 %sext82, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %sw.epilog
%and33 = and i32 %conv29, 32767
%sub34 = sub nsw i32 %a, %and33
br label %cond.end
cond.false: ; preds = %sw.epilog
%add37 = add nsw i32 %conv29, %a
br label %cond.end
; CHECK: @test
; CHECK: add [[REG:[0-9]+]],
; CHECK: subf [[REG2:[0-9]+]],
; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
%sext83 = shl i32 %cond, 16
%conv39 = ashr exact i32 %sext83, 16
%add41 = sub i32 %b, %a
%sub43 = add i32 %add41, %conv39
ret i32 %sub43
}