1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-18 18:42:46 +02:00
llvm-mirror/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
Amara Emerson 19a1782c85 [AArch64][GlobalISel] Flesh out vector load/store support for more types.
Some of these were legalizing into smaller vector types unnecessarily,
others were simply not supported yet.

llvm-svn: 358223
2019-04-11 20:40:01 +00:00

43 lines
1.3 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s
---
name: load_v4s32
legalized: false
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: load_v4s32
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: G_STORE [[LOAD]](<4 x s32>), [[COPY1]](p0) :: (store 16)
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
G_STORE %2(<4 x s32>), %1(p0) :: (store 16)
...
---
name: load_v2s64
legalized: false
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: load_v2s64
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: G_STORE [[LOAD]](<2 x s64>), [[COPY1]](p0) :: (store 16)
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
G_STORE %2(<2 x s64>), %1(p0) :: (store 16)
...