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Summary: Adds the following inline asm constraints for SVE: - w: SVE vector register with full range, Z0 to Z31 - x: Restricted to registers Z0 to Z15 inclusive. - y: Restricted to registers Z0 to Z7 inclusive. This change also adds the "z" modifier to interpret a register as an SVE register. Not all of the bitconvert patterns added by this patch are used, but they have been included here for completeness. Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, rengolin, cameron.mcinally, greened Reviewed By: sdesmalen Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66302 llvm-svn: 370673
13 lines
566 B
LLVM
13 lines
566 B
LLVM
; RUN: not llc -mtriple aarch64-none-linux-gnu -mattr=+neon -o %t.s -filetype=asm %s 2>&1 | FileCheck %s
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; The 'y' constraint only applies to SVE vector registers (Z0-Z7)
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; The test below ensures that we get an appropriate error should the
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; constraint be used with a Neon register.
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; Function Attrs: nounwind readnone
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; CHECK: error: couldn't allocate input reg for constraint 'y'
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define <4 x i32> @test_neon(<4 x i32> %in1, <4 x i32> %in2) {
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%1 = tail call <4 x i32> asm "add $0.4s, $1.4s, $2.4s", "=w,w,y"(<4 x i32> %in1, <4 x i32> %in2)
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ret <4 x i32> %1
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}
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