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0792d88e71
SplitVecOp_TruncateHelper tries to promote the result type while splitting FP_TO_SINT/UINT. It then concatenates the result and introduces a truncate to the original result type. But it does this without inserting the AssertZExt/AssertSExt that the regular result type promotion would insert. Nor does it turn FP_TO_UINT into FP_TO_SINT the way normal result type promotion for these operations does. This is bad on X86 which doesn't support FP_TO_SINT until AVX512. This patch disables the use of SplitVecOp_TruncateHelper for these operations and just lets normal promotion handle it. I've tweaked a couple things in X86ISelLowering to avoid a few obvious regressions there. I believe all the changes on X86 are improvements. The other targets look neutral. Differential Revision: https://reviews.llvm.org/D54906 llvm-svn: 347593
18 lines
748 B
LLVM
18 lines
748 B
LLVM
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define <8 x i8> @float_to_i8(<8 x float>* %in) {
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; CHECK-LABEL: float_to_i8:
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; CHECK: ldp q0, q1, [x0]
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; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s
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; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s
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; CHECK-DAG: fcvtzs v[[LSB2:[0-9]+]].4s, v[[LSB]].4s
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; CHECK-DAG: fcvtzs v[[MSB2:[0-9]+]].4s, v[[MSB]].4s
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; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s
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; CHECK-DAG: xtn v[[TMP2:[0-9]+]].4h, v[[MSB]].4s
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; CHECK-DAG: uzp1 v0.8b, v[[TMP]].8b, v[[TMP2]].8b
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%l = load <8 x float>, <8 x float>* %in
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%scale = fmul <8 x float> %l, <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>
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%conv = fptoui <8 x float> %scale to <8 x i8>
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ret <8 x i8> %conv
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}
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