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25d4c77ffe
Summary: If an MIMG instruction has managed to get through to adjustWritemask in isel but has no uses (and doesn't enable TFC) then prevent an assertion by not attempting to adjust the writemask. The instruction will be removed anyway. Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7 Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58964 llvm-svn: 356540
23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
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; We're really just checking for no crashes
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; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
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; In reality, it's hard to get an image intrinsic into AdjustWriteMask with no uses as it will usually get removed
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; first, but it can happen, hence the fix associated with this test
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; GCN-LABEL: name: _amdgpu_cs_main
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; GCN-LABEL: bb.0
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; GCN: IMAGE_LOAD_V4_V2
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define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
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.entry:
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%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
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call void asm sideeffect ";", "" () #0
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ret void
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}
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; Function Attrs: nounwind readonly
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declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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