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https://github.com/RPCS3/llvm-mirror.git
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216a9fc9a1
Summary: The symbols use the processor-specific SHN_AMDGPU_LDS section index introduced with a previous change. The linker is then expected to resolve relocations, which are also emitted. Initially disabled for HSA and PAL environments until they have caught up in terms of linker and runtime loader. Some notes: - The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered to a constant at compile times, which means some tests can no longer be applied. The current "solution" is a terrible hack, but the intrinsic isn't used by Mesa, so we can keep it for now. - We no longer know the full LDS size per kernel at compile time, which means that we can no longer generate a relevant error message at compile time. It would be possible to add a check for the size of individual variables, but ultimately the linker will have to perform the final check. Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275 Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61494 llvm-svn: 364297
438 lines
21 KiB
LLVM
438 lines
21 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,CIVI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
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declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
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declare i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
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declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
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declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
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declare i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; GCN-LABEL: {{^}}lds_atomic_dec_ret_i32:
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; CIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
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define amdgpu_kernel void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_dec_ret_i32_offset:
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; CIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] offset:16
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define amdgpu_kernel void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %gep, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_dec_noret_i32:
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; CIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
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; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
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; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; GCN: ds_dec_u32 [[VPTR]], [[DATA]]
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define amdgpu_kernel void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}lds_atomic_dec_noret_i32_offset:
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; CIVI-DAG: s_mov_b32 m0
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; GFX9-NOT: m0
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: ds_dec_u32 v{{[0-9]+}}, [[K]] offset:16
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define amdgpu_kernel void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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%gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %gep, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_ret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
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; GFX9: global_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]], off glc{{$}}
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define amdgpu_kernel void @global_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_ret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 glc{{$}}
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; GFX9: global_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]], off offset:16 glc{{$}}
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define amdgpu_kernel void @global_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_noret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
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; GFX9: global_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]], off{{$}}
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define amdgpu_kernel void @global_atomic_dec_noret_i32(i32 addrspace(1)* %ptr) nounwind {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_noret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}}
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; GFX9: global_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]], off offset:16{{$}}
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define amdgpu_kernel void @global_atomic_dec_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind {
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%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_ret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CI: buffer_atomic_dec [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20 glc{{$}}
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; VI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
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define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id
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%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_dec_noret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CI: buffer_atomic_dec [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}}
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; VI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
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define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
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%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32* %out
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
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; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr) #0 {
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%gep = getelementptr i32, i32* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32* %out
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
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define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
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; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}}
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define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32* %ptr) nounwind {
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%gep = getelementptr i32, i32* %ptr, i32 4
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
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; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32* %ptr, i32 %id
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%out.gep = getelementptr i32, i32* %out, i32 %id
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%gep = getelementptr i32, i32* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
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store i32 %result, i32* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64:
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
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; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
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; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}}
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define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i32, i32* %ptr, i32 %id
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%gep = getelementptr i32, i32* %gep.tid, i32 5
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%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {
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%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
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store i64 %result, i64* %out
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
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; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 {
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%gep = getelementptr i64, i64* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
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store i64 %result, i64* %out
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
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define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {
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%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset:
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; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
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; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
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define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind {
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%gep = getelementptr i64, i64* %ptr, i32 4
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%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64:
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; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
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; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}}
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define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.tid = getelementptr i64, i64* %ptr, i32 %id
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%out.gep = getelementptr i64, i64* %out, i32 %id
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%gep = getelementptr i64, i64* %gep.tid, i32 5
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%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
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store i64 %result, i64* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64:
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; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
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; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
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; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
|
|
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}}
|
|
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 {
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.tid = getelementptr i64, i64* %ptr, i32 %id
|
|
%gep = getelementptr i64, i64* %gep.tid, i32 5
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
@lds0 = addrspace(3) global [512 x i32] undef
|
|
|
|
; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; CIVI-DAG: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 2, {{v[0-9]+}}
|
|
; CIVI-DAG: v_add_{{[ui]}}32_e32 [[PTR:v[0-9]+]], vcc, lds0@abs32@lo, [[OFS]]
|
|
; GFX9-DAG: s_mov_b32 [[BASE:s[0-9]+]], lds0@abs32@lo
|
|
; GFX9-DAG: v_lshl_add_u32 [[PTR:v[0-9]+]], {{v[0-9]+}}, 2, [[BASE]]
|
|
|
|
; GCN: ds_dec_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
|
|
define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
|
|
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
%idx.0 = add nsw i32 %tid.x, 2
|
|
%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds0, i32 0, i32 %idx.0
|
|
%val0 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %arrayidx0, i32 9, i32 0, i32 0, i1 false)
|
|
store i32 %idx.0, i32 addrspace(1)* %add_use
|
|
store i32 %val0, i32 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
|
|
define amdgpu_kernel void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64_offset:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32
|
|
define amdgpu_kernel void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 {
|
|
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
|
|
define amdgpu_kernel void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind {
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}lds_atomic_dec_noret_i64_offset:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
|
|
define amdgpu_kernel void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
|
|
%gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64:
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}}
|
|
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off glc{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset:
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}}
|
|
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off offset:32 glc{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
|
|
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64:
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
|
|
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) nounwind {
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset:
|
|
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CIVI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}}
|
|
; GFX9: global_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off offset:32{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind {
|
|
%gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset_addr64:
|
|
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
|
|
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}}
|
|
; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
|
|
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
|
|
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
store i64 %result, i64 addrspace(1)* %out.gep
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset_addr64:
|
|
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
|
|
; CI: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
|
|
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
|
|
; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}}
|
|
; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}}
|
|
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
|
|
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
|
|
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
|
|
ret void
|
|
}
|
|
|
|
@lds1 = addrspace(3) global [512 x i64] undef, align 8
|
|
|
|
; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0_i64:
|
|
; CIVI-DAG: s_mov_b32 m0
|
|
; GFX9-NOT: m0
|
|
|
|
; CIVI-DAG: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 3, {{v[0-9]+}}
|
|
; CIVI-DAG: v_add_{{[ui]}}32_e32 [[PTR:v[0-9]+]], vcc, lds1@abs32@lo, [[OFS]]
|
|
; GFX9-DAG: v_mov_b32_e32 [[BASE:v[0-9]+]], lds1@abs32@lo
|
|
; GFX9-DAG: v_lshl_add_u32 [[PTR:v[0-9]+]], {{v[0-9]+}}, 3, [[BASE]]
|
|
|
|
; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16
|
|
define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
|
|
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
|
|
%idx.0 = add nsw i32 %tid.x, 2
|
|
%arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0
|
|
%val0 = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9, i32 0, i32 0, i1 false)
|
|
store i32 %idx.0, i32 addrspace(1)* %add_use
|
|
store i64 %val0, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|
|
attributes #2 = { nounwind argmemonly }
|