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6ac0148c30
Since the beginning, the offset of a frame index has been consistently interpreted backwards. It was treating it as an offset from the scratch wave offset register as a frame register. The correct interpretation is the offset from the SP on entry to the function, before the prolog. Frame index elimination then should select either SP or another register as an FP. Treat the scratch wave offset on kernel entry as the pre-incremented SP. Rely more heavily on the standard hasFP and frame pointer elimination logic, and clean up the private reservation code. This saves a copy in most callee functions. The kernel prolog emission code is still kind of a mess relying on checking the uses of physical registers, which I would prefer to eliminate. Currently selection directly emits MUBUF instructions, which require using a reference to some register. Use the register chosen for SP, and then ignore this later. This should probably be cleaned up to use pseudos that don't refer to any specific base register until frame index elimination. Add a workaround for shaders using large numbers of SGPRs. I'm not sure these cases were ever working correctly, since as far as I can tell the logic for figuring out which SGPR is the scratch wave offset doesn't match up with the shader input initialization in the shader programming guide. llvm-svn: 362661
103 lines
4.7 KiB
LLVM
103 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=MESA3D,ALL %s
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; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefixes=UNKNOWN,ALL %s
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; Make sure shaders pick a workable SP with > 32 input SGPRs.
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; FIXME: Doesn't seem to be getting initial value from right register?
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; ALL-LABEL: {{^}}too_many_input_sgprs_32:
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; MESA3D-NOT: s34
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; MESA3D: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s34 offset:4
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; Happens to end up in s32 anyway
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; UNKNOWN-NOT: s32
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; UNKNOWN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:4
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define amdgpu_ps i32 @too_many_input_sgprs_32(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7,
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i32 inreg %arg8, i32 inreg %arg9, i32 inreg %arg10, i32 inreg %arg11, i32 inreg %arg12, i32 inreg %arg13, i32 inreg %arg14, i32 inreg %arg15,
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i32 inreg %arg16, i32 inreg %arg17, i32 inreg %arg18, i32 inreg %arg19, i32 inreg %arg20, i32 inreg %arg21, i32 inreg %arg22, i32 inreg %arg23,
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i32 inreg %arg24, i32 inreg %arg25, i32 inreg %arg26, i32 inreg %arg27, i32 inreg %arg28, i32 inreg %arg29, i32 inreg %arg30, i32 inreg %arg31) {
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bb:
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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%tmp = add i32 %arg, %arg1
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%tmp32 = add i32 %tmp, %arg2
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%tmp33 = add i32 %tmp32, %arg3
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%tmp34 = add i32 %tmp33, %arg4
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%tmp35 = add i32 %tmp34, %arg5
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%tmp36 = add i32 %tmp35, %arg6
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%tmp37 = add i32 %tmp36, %arg7
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%tmp38 = add i32 %tmp37, %arg8
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%tmp39 = add i32 %tmp38, %arg9
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%tmp40 = add i32 %tmp39, %arg10
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%tmp41 = add i32 %tmp40, %arg11
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%tmp42 = add i32 %tmp41, %arg12
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%tmp43 = add i32 %tmp42, %arg13
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%tmp44 = add i32 %tmp43, %arg14
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%tmp45 = add i32 %tmp44, %arg15
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%tmp46 = add i32 %tmp45, %arg16
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%tmp47 = add i32 %tmp46, %arg17
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%tmp48 = add i32 %tmp47, %arg18
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%tmp49 = add i32 %tmp48, %arg19
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%tmp50 = add i32 %tmp49, %arg20
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%tmp51 = add i32 %tmp50, %arg21
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%tmp52 = add i32 %tmp51, %arg22
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%tmp53 = add i32 %tmp52, %arg23
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%tmp54 = add i32 %tmp53, %arg24
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%tmp55 = add i32 %tmp54, %arg25
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%tmp56 = add i32 %tmp55, %arg26
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%tmp57 = add i32 %tmp56, %arg27
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%tmp58 = add i32 %tmp57, %arg28
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%tmp59 = add i32 %tmp58, %arg29
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%tmp60 = add i32 %tmp59, %arg30
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%tmp61 = add i32 %tmp60, %arg31
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ret i32 %tmp61
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}
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; ALL-LABEL: {{^}}too_many_input_sgprs_33:
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; MESA3D-NOT: s35
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; MESA3D: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s35 offset:4
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; UNKNOWN-NOT: s33
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; UNKNOWN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s33 offset:4
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define amdgpu_ps i32 @too_many_input_sgprs_33(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, i32 inreg %arg3, i32 inreg %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 inreg %arg7,
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i32 inreg %arg8, i32 inreg %arg9, i32 inreg %arg10, i32 inreg %arg11, i32 inreg %arg12, i32 inreg %arg13, i32 inreg %arg14, i32 inreg %arg15,
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i32 inreg %arg16, i32 inreg %arg17, i32 inreg %arg18, i32 inreg %arg19, i32 inreg %arg20, i32 inreg %arg21, i32 inreg %arg22, i32 inreg %arg23,
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i32 inreg %arg24, i32 inreg %arg25, i32 inreg %arg26, i32 inreg %arg27, i32 inreg %arg28, i32 inreg %arg29, i32 inreg %arg30, i32 inreg %arg31,
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i32 inreg %arg32) {
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bb:
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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%tmp = add i32 %arg, %arg1
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%tmp32 = add i32 %tmp, %arg2
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%tmp33 = add i32 %tmp32, %arg3
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%tmp34 = add i32 %tmp33, %arg4
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%tmp35 = add i32 %tmp34, %arg5
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%tmp36 = add i32 %tmp35, %arg6
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%tmp37 = add i32 %tmp36, %arg7
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%tmp38 = add i32 %tmp37, %arg8
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%tmp39 = add i32 %tmp38, %arg9
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%tmp40 = add i32 %tmp39, %arg10
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%tmp41 = add i32 %tmp40, %arg11
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%tmp42 = add i32 %tmp41, %arg12
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%tmp43 = add i32 %tmp42, %arg13
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%tmp44 = add i32 %tmp43, %arg14
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%tmp45 = add i32 %tmp44, %arg15
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%tmp46 = add i32 %tmp45, %arg16
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%tmp47 = add i32 %tmp46, %arg17
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%tmp48 = add i32 %tmp47, %arg18
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%tmp49 = add i32 %tmp48, %arg19
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%tmp50 = add i32 %tmp49, %arg20
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%tmp51 = add i32 %tmp50, %arg21
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%tmp52 = add i32 %tmp51, %arg22
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%tmp53 = add i32 %tmp52, %arg23
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%tmp54 = add i32 %tmp53, %arg24
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%tmp55 = add i32 %tmp54, %arg25
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%tmp56 = add i32 %tmp55, %arg26
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%tmp57 = add i32 %tmp56, %arg27
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%tmp58 = add i32 %tmp57, %arg28
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%tmp59 = add i32 %tmp58, %arg29
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%tmp60 = add i32 %tmp59, %arg30
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%tmp61 = add i32 %tmp60, %arg31
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%tmp62 = add i32 %tmp61, %arg32
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ret i32 %tmp62
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}
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