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llvm-mirror/test/CodeGen/AMDGPU/verify-sop.mir
Nicolai Haehnle 2cbea0cdd9 AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand
Summary:
No test case because I don't know of a way to trigger this, but I
accidentally caused this to fail while working on a different change.

Change-Id: I8015aa447fe27163cc4e4902205a203bd44bf7e3

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61490

llvm-svn: 360123
2019-05-07 09:19:09 +00:00

22 lines
664 B
YAML

# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s
# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
# CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32
# CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
# CHECK: - instruction: S_CMP_EQ_U32
# CHECK-NOT: Bad machine code
---
name: sop2_sopc
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32_xm0 = S_ADD_I32 2011, -113, implicit-def $scc
S_CMP_EQ_U32 2011, -113, implicit-def $scc
%1:sreg_32_xm0 = S_SUB_I32 2011, 10, implicit-def $scc
S_CMP_LG_U32 -5, 2011, implicit-def $scc
...