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db3c93e416
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
55 lines
1.5 KiB
LLVM
55 lines
1.5 KiB
LLVM
; RUN: llc -march=hexagon -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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; REQUIRES: asserts
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; Check for some output other than crashing.
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; CHECK: bitsset
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @fred() local_unnamed_addr #0 {
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b0:
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%v1 = load i32, i32* undef, align 4
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%v2 = and i32 %v1, 603979776
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%v3 = trunc i32 %v2 to i30
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switch i30 %v3, label %b23 [
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i30 -536870912, label %b4
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i30 -469762048, label %b5
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]
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b4: ; preds = %b0
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unreachable
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b5: ; preds = %b0
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%v6 = load i32, i32* undef, align 4
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br i1 undef, label %b7, label %b8
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b7: ; preds = %b5
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br label %b9
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b8: ; preds = %b5
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br label %b9
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b9: ; preds = %b8, %b7
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%v10 = load i32, i32* undef, align 4
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%v11 = load i32, i32* undef, align 4
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%v12 = mul nsw i32 %v11, %v10
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%v13 = ashr i32 %v12, 13
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%v14 = mul nsw i32 %v13, %v13
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%v15 = zext i32 %v14 to i64
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%v16 = mul nsw i32 %v6, %v6
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%v17 = zext i32 %v16 to i64
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%v18 = lshr i64 %v17, 5
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%v19 = select i1 undef, i64 %v18, i64 %v17
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%v20 = mul nuw nsw i64 %v19, %v15
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%v21 = trunc i64 %v20 to i32
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%v22 = and i32 %v21, 2147483647
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store i32 %v22, i32* undef, align 4
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unreachable
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b23: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
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