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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
53 lines
1.8 KiB
LLVM
53 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon -O3 -verify-machineinstrs < %s | FileCheck %s
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; REQUIRES: asserts
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; Check for sane output. This testcase used to crash.
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; CHECK: jumpr r31
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target triple = "hexagon"
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@g0 = external hidden unnamed_addr constant [9 x i16], align 8
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; Function Attrs: nounwind readnone
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define i64 @fred(i32 %a0) local_unnamed_addr #0 {
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b1:
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%v2 = icmp slt i32 %a0, 1
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br i1 %v2, label %b26, label %b3
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b3: ; preds = %b1
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%v4 = tail call i32 @llvm.hexagon.S2.clb(i32 %a0)
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%v5 = add nsw i32 %v4, -12
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%v6 = add nsw i32 %v4, -28
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%v7 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v6)
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%v8 = add nsw i32 %v7, -8
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%v9 = tail call i32 @llvm.hexagon.S2.asl.r.r(i32 %a0, i32 %v5)
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%v10 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v8
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%v11 = load i16, i16* %v10, align 2
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%v12 = sext i16 %v11 to i32
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%v13 = shl nsw i32 %v12, 16
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%v14 = add nsw i32 %v7, -7
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%v15 = getelementptr inbounds [9 x i16], [9 x i16]* @g0, i32 0, i32 %v14
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%v16 = load i16, i16* %v15, align 2
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%v17 = sub i16 %v11, %v16
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%v18 = and i32 %v9, 65535
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%v19 = zext i16 %v17 to i32
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%v20 = tail call i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32 %v13, i32 %v18, i32 %v19) #1
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%v21 = add nsw i32 %v4, -32
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%v22 = zext i32 %v21 to i64
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%v23 = shl nuw i64 %v22, 32
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%v24 = zext i32 %v20 to i64
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%v25 = or i64 %v23, %v24
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br label %b26
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b26: ; preds = %b3, %b1
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%v27 = phi i64 [ %v25, %b3 ], [ 2147483648, %b1 ]
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ret i64 %v27
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}
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declare i32 @llvm.hexagon.S2.clb(i32) #1
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declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1
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declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" }
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attributes #1 = { nounwind readnone }
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