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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
52 lines
1.9 KiB
LLVM
52 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; This used to crash.
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; CHECK: call f1
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target triple = "hexagon-unknown--elf"
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%struct.0 = type { [5 x i32] }
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%struct.2 = type { i32, i32, i32, %struct.1* }
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%struct.1 = type { i16*, i32, i32, i32 }
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@g0 = external hidden unnamed_addr constant [52 x i8], align 1
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@g1 = external hidden unnamed_addr constant [3 x i8], align 1
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declare extern_weak void @f0(i32, i8*, i32, i8*, ...) #0
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declare void @f1(%struct.0*, i32) #0
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define void @fred(i8* %a0) #0 {
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b1:
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%v2 = alloca %struct.0, align 4
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%v3 = alloca %struct.2, i32 undef, align 8
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br i1 undef, label %b5, label %b4
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b4: ; preds = %b1
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br label %b7
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b5: ; preds = %b5, %b1
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%v6 = getelementptr inbounds %struct.2, %struct.2* %v3, i32 undef, i32 3
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store %struct.1* undef, %struct.1** %v6, align 4
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br label %b5
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b7: ; preds = %b10, %b4
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%v8 = call i32 @llvm.hexagon.V6.extractw(<16 x i32> zeroinitializer, i32 0)
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br i1 icmp eq (void (i32, i8*, i32, i8*, ...)* @f0, void (i32, i8*, i32, i8*, ...)* null), label %b11, label %b9
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b9: ; preds = %b7
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call void (i32, i8*, i32, i8*, ...) @f0(i32 2, i8* getelementptr inbounds ([52 x i8], [52 x i8]* @g0, i32 0, i32 0), i32 2346, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @g1, i32 0, i32 0), i32 %v8)
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unreachable
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b10: ; preds = %b11
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call void @f1(%struct.0* nonnull %v2, i32 28)
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br label %b7
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b11: ; preds = %b11, %b7
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br i1 undef, label %b10, label %b11
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}
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declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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