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3880641c3c
The Verifier is separate from the MachineVerifier, so move it to a different directory. Some other verifier tests were scattered in target codegen tests as well (although I'm sure I missed some). Work towards using a more consistent naming scheme to make it clearer where the gaps still are for generic instructions. llvm-svn: 354138
38 lines
1.0 KiB
YAML
38 lines
1.0 KiB
YAML
#RUN: not llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: global-isel, aarch64-registered-target
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---
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name: test_add
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0:
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = G_CONSTANT i32 1
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; CHECK: Bad machine code: Too few operands
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%2:_(s32) = G_ADD
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; CHECK: Bad machine code: Too few operands
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%3:_(s32) = G_ADD %0
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%4:_(s32) = G_ADD %0, %1
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; CHECK: Bad machine code: Too few operands
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; CHECK: Bad machine code: Explicit definition marked as use
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G_ADD %0, %1
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; CHECK: Bad machine code: generic instruction must use register operands
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%5:_(s32) = G_ADD %0, 1
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%6:_(s64) = G_CONSTANT i64 0
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; CHECK: Bad machine code: Type mismatch in generic instruction
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; CHECK: Bad machine code: Generic virtual register does not allow subregister index
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%8:_(s32) = G_ADD %6.sub_32:_(s64), %0
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...
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