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710eb84124
This patch is the initial support for the Intial Exec Thread Local Local Storage model to produce code sequence and relocations correct to the ABI for the model when using PC relative memory operations. Reviewed By: stefanp Differential Revision: https://reviews.llvm.org/D81947
49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -enable-ppc-pcrel-tls < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-S
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names --filetype=obj \
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; RUN: -enable-ppc-pcrel-tls < %s | llvm-objdump --mcpu=pwr10 -dr - | \
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; RUN: FileCheck %s --check-prefix=CHECK-O
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; These test cases are to ensure that when using pc relative memory operations
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; ABI correct code and relocations are produced for Initial Exec TLS Model.
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; Note that with R_PPC64_TLS relocations, to distinguish PC relative
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; TLS the relocation has a field value displaced by one byte from the
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; beginning of the instruction.
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@x = external thread_local global i32, align 4
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define i32* @InitialExecAddressLoad() {
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; CHECK-S-LABEL: InitialExecAddressLoad:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: pld r3, x@got@tprel@pcrel(0), 1
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; CHECK-S-NEXT: add r3, r3, x@tls@pcrel
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <InitialExecAddressLoad>:
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; CHECK-O: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1
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; CHECK-O-NEXT: 0000000000000000: R_PPC64_GOT_TPREL_PCREL34 x
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; CHECK-O-NEXT: 14 6a 63 7c add 3, 3, 13
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; CHECK-O-NEXT: 0000000000000009: R_PPC64_TLS x
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; CHECK-O-NEXT: 20 00 80 4e blr
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entry:
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ret i32* @x
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}
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define i32 @InitialExecValueLoad() {
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; CHECK-S-LABEL: InitialExecValueLoad:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: pld r3, x@got@tprel@pcrel(0), 1
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; CHECK-S-NEXT: lwzx r3, r3, x@tls@pcrel
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <InitialExecValueLoad>:
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; CHECK-O: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1
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; CHECK-O-NEXT: 0000000000000020: R_PPC64_GOT_TPREL_PCREL34 x
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; CHECK-O-NEXT: 2e 68 63 7c lwzx 3, 3, 13
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; CHECK-O-NEXT: 0000000000000029: R_PPC64_TLS x
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; CHECK-O-NEXT: 20 00 80 4e blr
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entry:
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%0 = load i32, i32* @x, align 4
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ret i32 %0
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}
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