Mandeep Singh Grang fad0fd9a71 [RISCV] Use init_array instead of ctors for RISCV target, by default ... Summary: LLVM defaults to the newer .init_array/.fini_array scheme for static constructors rather than the less desirable .ctors/.dtors (the UseCtors flag defaults to false). This wasn't being respected in the RISC-V backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate flag for UseInitArray. This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call InitializeELF(TM.Options.UseInitArray). Reviewers: asb, apazos Reviewed By: asb Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits Differential Revision: https://reviews.llvm.org/D44750 llvm-svn: 328433		2018-03-24 18:37:19 +00:00
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AsmParser	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
Disassembler	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
InstPrinter	[RISCV] Pass MCSubtargetInfo to print methods.	2018-01-12 02:27:00 +00:00
MCTargetDesc	[RISCV] Implement MC relaxations for compressed instructions.	2018-03-02 22:04:12 +00:00
TargetInfo	Fix RISCV build after r318352	2017-11-16 18:39:31 +00:00
CMakeLists.txt	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
LLVMBuild.txt	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCV.h	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
RISCV.td	[MachineOperand][Target] MachineOperand::isRenamable semantics changes	2018-02-23 18:25:08 +00:00
RISCVAsmPrinter.cpp	[RISCV] Add basic support for inline asm constraints	2018-01-10 20:05:09 +00:00
RISCVCallingConv.td	[RISCV] Add custom CC_RISCV calling convention and improved call support	2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVFrameLowering.h	[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects	2018-03-20 01:39:17 +00:00
RISCVInstrFormats.td	[RISCV] MC layer support for load/store instructions of the C (compressed) extension	2017-12-07 12:50:32 +00:00
RISCVInstrFormatsC.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfo.h	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVInstrInfo.td	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfoA.td	[RISCV] MC layer support for the standard RV64A instruction set extension	2017-12-07 10:59:12 +00:00
RISCVInstrInfoC.td	[RISCV] Implement c.lui immediate operand constraint	2018-02-22 15:02:28 +00:00
RISCVInstrInfoD.td	[RISCV] Implement floating point assembler pseudo instructions	2017-12-13 11:37:19 +00:00
RISCVInstrInfoF.td	[RISCV] Codegen support for RV32F floating point comparison operations	2018-03-21 15:11:02 +00:00
RISCVInstrInfoM.td	[RISCV] Codegen support for the standard RV32M instruction set extension	2018-01-18 12:36:38 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Peephole optimisation for load/store of global values or constant addresses	2018-03-19 11:54:28 +00:00
RISCVISelLowering.cpp	Fix layering by moving ValueTypes.h from CodeGen to IR	2018-03-23 23:58:31 +00:00
RISCVISelLowering.h	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Support for varargs	2018-01-10 19:41:03 +00:00
RISCVMCInstLower.cpp	[RISCV] Add codegen for RV32F floating point load/store	2018-03-20 13:26:12 +00:00
RISCVRegisterInfo.cpp	[RISCV] Implement frame pointer elimination	2018-01-18 11:34:02 +00:00
RISCVRegisterInfo.h	[RISCV] Implement support for the BranchRelaxation pass	2018-01-10 21:05:07 +00:00
RISCVRegisterInfo.td	[RISCV] MC layer support for the remaining RVC instructions	2017-12-13 09:32:55 +00:00
RISCVSubtarget.cpp	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVSubtarget.h	[RISCV] MC layer support for load/store instructions of the C (compressed) extension	2017-12-07 12:50:32 +00:00
RISCVTargetMachine.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetMachine.h	[RISCV] Initial codegen support for ALU operations	2017-10-19 21:37:38 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h	[RISCV] Use init_array instead of ctors for RISCV target, by default	2018-03-24 18:37:19 +00:00