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fb0ed4b40d
Unlike Neon, MVE does not have a way of duplicating from a vector lane, so a VDUPLANE currently selects to a VDUP(move_from_lane(..)). This forces that to be done earlier as a dag combine to allow other folds to happen. It converts to a VDUP(EXTRACT). On FP16 this is then folded to a VGETLANEu to prevent it from creating a vmovx;vmovhr pair, using a single move_from_reg instead. Differential Revision: https://reviews.llvm.org/D79606
272 lines
8.8 KiB
LLVM
272 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @vdup_i32(i32 %src) {
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; CHECK-LABEL: vdup_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <4 x i32> undef, i32 %src, i32 0
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%out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vdup_i16(i16 %src) {
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; CHECK-LABEL: vdup_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <8 x i16> undef, i16 %src, i32 0
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%out = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i8> @vdup_i8(i8 %src) {
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; CHECK-LABEL: vdup_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdup.8 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <16 x i8> undef, i8 %src, i32 0
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%out = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %out
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}
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define arm_aapcs_vfpcc <2 x i64> @vdup_i64(i64 %src) {
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; CHECK-LABEL: vdup_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.32 q0[0], r0
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; CHECK-NEXT: vmov.32 q0[1], r1
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; CHECK-NEXT: vmov.32 q0[2], r0
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; CHECK-NEXT: vmov.32 q0[3], r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <2 x i64> undef, i64 %src, i32 0
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%out = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %out
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}
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define arm_aapcs_vfpcc <4 x float> @vdup_f32_1(float %src) {
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; CHECK-LABEL: vdup_f32_1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <4 x float> undef, float %src, i32 0
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%out = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %out
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}
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define arm_aapcs_vfpcc <4 x float> @vdup_f32_2(float %src1, float %src2) {
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; CHECK-LABEL: vdup_f32_2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.f32 s0, s0, s1
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = fadd float %src1, %src2
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%1 = insertelement <4 x float> undef, float %0, i32 0
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%out = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %out
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}
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define arm_aapcs_vfpcc <4 x float> @vdup_f32_1bc(float %src) {
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; CHECK-LABEL: vdup_f32_1bc:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%srcbc = bitcast float %src to i32
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%0 = insertelement <4 x i32> undef, i32 %srcbc, i32 0
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%out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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%outbc = bitcast <4 x i32> %out to <4 x float>
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ret <4 x float> %outbc
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}
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define arm_aapcs_vfpcc <4 x float> @vdup_f32_2bc(float %src1, float %src2) {
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; CHECK-LABEL: vdup_f32_2bc:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vadd.f32 s0, s0, s1
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = fadd float %src1, %src2
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%bc = bitcast float %0 to i32
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%1 = insertelement <4 x i32> undef, i32 %bc, i32 0
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%out = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer
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%outbc = bitcast <4 x i32> %out to <4 x float>
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ret <4 x float> %outbc
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}
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; TODO: Calling convention needs fixing to pass half types directly to functions
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define arm_aapcs_vfpcc <8 x half> @vdup_f16(half* %src1, half* %src2) {
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; CHECK-LABEL: vdup_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s0, [r1]
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; CHECK-NEXT: vldr.16 s2, [r0]
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; CHECK-NEXT: vadd.f16 s0, s2, s0
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; CHECK-NEXT: vmov.f16 r0, s0
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = load half, half *%src1, align 2
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%1 = load half, half *%src2, align 2
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%2 = fadd half %0, %1
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%3 = insertelement <8 x half> undef, half %2, i32 0
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%out = shufflevector <8 x half> %3, <8 x half> undef, <8 x i32> zeroinitializer
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @vdup_f16_bc(half* %src1, half* %src2) {
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; CHECK-LABEL: vdup_f16_bc:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s0, [r1]
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; CHECK-NEXT: vldr.16 s2, [r0]
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; CHECK-NEXT: vadd.f16 s0, s2, s0
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; CHECK-NEXT: vmov.f16 r0, s0
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = load half, half *%src1, align 2
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%1 = load half, half *%src2, align 2
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%2 = fadd half %0, %1
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%bc = bitcast half %2 to i16
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%3 = insertelement <8 x i16> undef, i16 %bc, i32 0
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%out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer
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%outbc = bitcast <8 x i16> %out to <8 x half>
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ret <8 x half> %outbc
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}
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define arm_aapcs_vfpcc <2 x double> @vdup_f64(double %src) {
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; CHECK-LABEL: vdup_f64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: vmov.f32 s2, s0
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; CHECK-NEXT: vmov.f32 s3, s1
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; CHECK-NEXT: bx lr
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entry:
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%0 = insertelement <2 x double> undef, double %src, i32 0
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%out = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
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ret <2 x double> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @vduplane_i32(<4 x i32> %src) {
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; CHECK-LABEL: vduplane_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @vduplane_i16(<8 x i16> %src) {
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; CHECK-LABEL: vduplane_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[3]
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i8> @vduplane_i8(<16 x i8> %src) {
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; CHECK-LABEL: vduplane_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u8 r0, q0[3]
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; CHECK-NEXT: vdup.8 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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ret <16 x i8> %out
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}
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define arm_aapcs_vfpcc <2 x i64> @vduplane_i64(<2 x i64> %src) {
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; CHECK-LABEL: vduplane_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s0, s2
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; CHECK-NEXT: vmov.f32 s1, s3
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %out
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}
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define arm_aapcs_vfpcc <4 x float> @vduplane_f32(<4 x float> %src) {
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; CHECK-LABEL: vduplane_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vdup.32 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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ret <4 x float> %out
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}
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define arm_aapcs_vfpcc <8 x half> @vduplane_f16(<8 x half> %src) {
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; CHECK-LABEL: vduplane_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.u16 r0, q0[3]
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; CHECK-NEXT: vdup.16 q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <2 x double> @vduplane_f64(<2 x double> %src) {
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; CHECK-LABEL: vduplane_f64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s0, s2
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; CHECK-NEXT: vmov.f32 s1, s3
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <2 x double> %src, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %out
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}
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define arm_aapcs_vfpcc float @vdup_f32_extract(float %src) {
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; CHECK-LABEL: vdup_f32_extract:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%srcbc = bitcast float %src to i32
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%0 = insertelement <4 x i32> undef, i32 %srcbc, i32 0
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%out = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
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%outbc = bitcast <4 x i32> %out to <4 x float>
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%ext = extractelement <4 x float> %outbc, i32 2
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ret float %ext
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}
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define arm_aapcs_vfpcc half @vdup_f16_extract(half* %src1, half* %src2) {
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; CHECK-LABEL: vdup_f16_extract:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s0, [r2]
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; CHECK-NEXT: vldr.16 s2, [r1]
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; CHECK-NEXT: vadd.f16 s0, s2, s0
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; CHECK-NEXT: vstr.16 s0, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load half, half *%src1, align 2
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%1 = load half, half *%src2, align 2
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%2 = fadd half %0, %1
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%bc = bitcast half %2 to i16
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%3 = insertelement <8 x i16> undef, i16 %bc, i32 0
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%out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer
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%outbc = bitcast <8 x i16> %out to <8 x half>
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%ext = extractelement <8 x half> %outbc, i32 2
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ret half %ext
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}
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