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3a9a1ac61b
For some reason there are both of these available, except for scalar 64-bit compares which only has u64. I'm not sure why there are both (I'm guessing it's for the one bit inputs we don't use), but for consistency always using the unsigned one. llvm-svn: 282832
179 lines
8.1 KiB
LLVM
179 lines
8.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s
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; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s
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; FIXME: Enable for VI.
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone
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declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone
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; GCN-LABEL: {{^}}test_div_fmas_f32:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
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; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
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; GCN: buffer_store_dword [[RESULT]],
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; GCN: s_endpgm
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define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0:
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; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
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; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
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; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
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; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
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; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f64:
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; GCN: v_div_fmas_f64
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define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
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%result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
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; SI: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}}
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
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%cmp = icmp eq i32 %i, 0
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
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; SI: s_mov_b64 vcc, 0
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
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; SI: s_mov_b64 vcc, -1
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
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; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
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; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
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; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
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; SI: s_endpgm
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define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
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%gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 2
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%a = load volatile float, float addrspace(1)* %gep.a
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%b = load volatile float, float addrspace(1)* %gep.b
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%c = load volatile float, float addrspace(1)* %gep.c
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%cmp0 = icmp eq i32 %tid, 0
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%cmp1 = icmp ne i32 %d, 0
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%and = and i1 %cmp0, %cmp1
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
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store float %result, float addrspace(1)* %gep.out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
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; SI: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
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; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
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; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]]
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; SI: buffer_load_dword [[LOAD:v[0-9]+]]
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; SI: v_cmp_ne_u32_e32 vcc, 0, [[LOAD]]
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; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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; SI: BB9_2:
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; SI: s_or_b64 exec, exec, [[SAVE]]
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; SI: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
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; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
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; SI: buffer_store_dword
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; SI: s_endpgm
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define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 2
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%gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
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%gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
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%gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
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%a = load float, float addrspace(1)* %gep.a
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%b = load float, float addrspace(1)* %gep.b
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%c = load float, float addrspace(1)* %gep.c
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%cmp0 = icmp eq i32 %tid, 0
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br i1 %cmp0, label %bb, label %exit
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bb:
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%val = load i32, i32 addrspace(1)* %dummy
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%cmp1 = icmp ne i32 %val, 0
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br label %exit
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exit:
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%cond = phi i1 [false, %entry], [%cmp1, %bb]
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%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
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store float %result, float addrspace(1)* %gep.out, align 4
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ret void
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}
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