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0fa09433f0
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
77 lines
3.3 KiB
LLVM
77 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
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; CHECK: test1
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; CHECK: movi d[[REG0:[0-9]+]], #0000000000000000
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define <8 x i1> @test1() {
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entry:
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%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
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i1 7>,
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<8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
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i1 7>,
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<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
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i32 12, i32 14, i32 0>
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ret <8 x i1> %Shuff
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}
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; CHECK: lCPI1_0:
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: test2
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; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_0@PAGE
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; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
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define <8 x i1>@test2() {
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bb:
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%Shuff = shufflevector <8 x i1> zeroinitializer,
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<8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
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<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
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i32 0>
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ret <8 x i1> %Shuff
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}
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; CHECK: test3
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; CHECK: movi.4s v{{[0-9]+}}, #1
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define <16 x i1> @test3(i1* %ptr, i32 %v) {
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bb:
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%Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
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<16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
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i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
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i32 14, i32 0>
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ret <16 x i1> %Shuff
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}
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; CHECK: lCPI3_0:
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 1 ; 0x1
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: .byte 0 ; 0x0
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; CHECK: _test4:
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; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE
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; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
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define <16 x i1> @test4(i1* %ptr, i32 %v) {
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bb:
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%Shuff = shufflevector <16 x i1> zeroinitializer,
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<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
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i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
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<16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
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i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
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ret <16 x i1> %Shuff
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}
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