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8181753289
This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 llvm-svn: 325653
1206 lines
49 KiB
TableGen
1206 lines
49 KiB
TableGen
def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;
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def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;
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def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;
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def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
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def simm9_addiusp : Operand<i32> {
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let EncoderMethod = "getSImm9AddiuspValue";
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let DecoderMethod = "DecodeSimm9SP";
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}
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def uimm3_shift : Operand<i32> {
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let EncoderMethod = "getUImm3Mod8Encoding";
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let DecoderMethod = "DecodePOOL16BEncodedField";
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}
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def simm3_lsa2 : Operand<i32> {
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let EncoderMethod = "getSImm3Lsa2Value";
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let DecoderMethod = "DecodeAddiur2Simm7";
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}
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def uimm4_andi : Operand<i32> {
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let EncoderMethod = "getUImm4AndValue";
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let DecoderMethod = "DecodeANDI16Imm";
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}
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def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
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((Imm % 4 == 0) &&
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Imm < 28 && Imm > 0);}]>;
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def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
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def immZExtAndi16 : ImmLeaf<i32,
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[{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
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Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
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Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
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def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
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def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
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def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
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let Name = "MicroMipsMem";
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let RenderMethod = "addMicroMipsMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithGRPMM16Base";
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}
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// Define the classes of pointers used by microMIPS.
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// The numbers must match those in MipsRegisterInfo::MipsPtrClass.
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def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
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def ptr_sp_rc : PointerLikeRegClass<2>;
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def ptr_gp_rc : PointerLikeRegClass<3>;
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class mem_mm_4_generic : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
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}
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def mem_mm_4 : mem_mm_4_generic {
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let EncoderMethod = "getMemEncodingMMImm4";
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}
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def mem_mm_4_lsl1 : mem_mm_4_generic {
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let EncoderMethod = "getMemEncodingMMImm4Lsl1";
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}
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def mem_mm_4_lsl2 : mem_mm_4_generic {
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let EncoderMethod = "getMemEncodingMMImm4Lsl2";
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}
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def MicroMipsMemSPAsmOperand : AsmOperandClass {
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let Name = "MicroMipsMemSP";
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
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}
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def MicroMipsMemGPAsmOperand : AsmOperandClass {
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let Name = "MicroMipsMemGP";
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithSimmWordAlignedOffsetGP<9>";
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}
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def mem_mm_sp_imm5_lsl2 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemSPAsmOperand;
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let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
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}
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def mem_mm_gp_simm7_lsl2 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_gp_rc:$base, simm7_lsl2:$offset);
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let OperandType = "OPERAND_MEMORY";
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let ParserMatchClass = MicroMipsMemGPAsmOperand;
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let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
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}
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def mem_mm_9 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm9);
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let EncoderMethod = "getMemEncodingMMImm9";
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let ParserMatchClass = MipsMemSimm9AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def mem_mm_11 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops GPR32, simm11);
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let EncoderMethod = "getMemEncodingMMImm11";
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let ParserMatchClass = MipsMemSimm11AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def mem_mm_12 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm12);
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let EncoderMethod = "getMemEncodingMMImm12";
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let ParserMatchClass = MipsMemAsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def mem_mm_16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm16);
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let EncoderMethod = "getMemEncodingMMImm16";
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let ParserMatchClass = MipsMemSimm16AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def MipsMemUimm4AsmOperand : AsmOperandClass {
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let Name = "MemOffsetUimm4";
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let SuperClasses = [MipsMemAsmOperand];
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let RenderMethod = "addMemOperands";
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let ParserMethod = "parseMemOperand";
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let PredicateMethod = "isMemWithUimmOffsetSP<6>";
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}
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def mem_mm_4sp : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_sp_rc, uimm8);
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let EncoderMethod = "getMemEncodingMMImm4sp";
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let ParserMatchClass = MipsMemUimm4AsmOperand;
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let OperandType = "OPERAND_MEMORY";
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}
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def jmptarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def calltarget_mm : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValueMM";
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}
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def brtarget7_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTarget7OpValueMM";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget7MM";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def brtarget10_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMMPC10";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget10MM";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def brtarget_mm : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValueMM";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTargetMM";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def simm23_lsl2 : Operand<i32> {
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let EncoderMethod = "getSimm23Lsl2Encoding";
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let DecoderMethod = "DecodeSimm23Lsl2";
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}
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class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
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RegisterOperand RO> :
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InstSE<(outs), (ins RO:$rs, opnd:$offset),
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!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 0;
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let Defs = [AT];
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}
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let canFoldAsLoad = 1 in
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class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd, InstrItinClass Itin> :
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InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
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Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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string Constraints = "$src = $rt";
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}
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class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
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Operand MemOpnd, InstrItinClass Itin>:
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InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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}
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/// A register pair used by movep instruction.
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def MovePRegPairAsmOperand : AsmOperandClass {
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let Name = "MovePRegPair";
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let ParserMethod = "parseMovePRegPair";
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let PredicateMethod = "isMovePRegPair";
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}
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def movep_regpair : Operand<i32> {
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let EncoderMethod = "getMovePRegPairOpValue";
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let ParserMatchClass = MovePRegPairAsmOperand;
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let PrintMethod = "printRegisterList";
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let DecoderMethod = "DecodeMovePRegPair";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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}
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class MovePMM16<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
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!strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
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NoItinerary, FrmR> {
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let isReMaterializable = 1;
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}
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/// A register pair used by load/store pair instructions.
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def RegPairAsmOperand : AsmOperandClass {
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let Name = "RegPair";
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let ParserMethod = "parseRegisterPair";
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let PredicateMethod = "isRegPair";
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}
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def regpair : Operand<i32> {
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let EncoderMethod = "getRegisterPairOpValue";
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let ParserMatchClass = RegPairAsmOperand;
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let PrintMethod = "printRegisterPair";
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let DecoderMethod = "DecodeRegPairOperand";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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}
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class StorePairMM<string opstr, ComplexPattern Addr = addr>
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: InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayStore = 1;
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}
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class LoadPairMM<string opstr, ComplexPattern Addr = addr>
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: InstSE<(outs regpair:$rt), (ins mem_simm12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayLoad = 1;
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}
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class LLBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayLoad = 1;
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}
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class LLEBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
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let DecoderMethod = "DecodeMemMMImm9";
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string BaseOpcode = opstr;
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let mayLoad = 1;
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}
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class SCBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
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let DecoderMethod = "DecodeMemMMImm12";
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let mayStore = 1;
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let Constraints = "$rt = $dst";
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}
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class SCEBaseMM<string opstr, RegisterOperand RO> :
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InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
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let DecoderMethod = "DecodeMemMMImm9";
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string BaseOpcode = opstr;
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let mayStore = 1;
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let Constraints = "$rt = $dst";
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}
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class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
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InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
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InstSE<(outs RO:$rt), (ins MO:$addr),
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!strconcat(opstr, "\t$rt, $addr"),
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[(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
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let DecoderMethod = "DecodeMemMMImm12";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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}
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class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
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InstrItinClass Itin = NoItinerary,
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SDPatternOperator OpNode = null_frag> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
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!strconcat(opstr, "\t$rd, $rs, $rt"),
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[(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
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let isCommutable = isComm;
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}
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class AndImmMM16<string opstr, RegisterOperand RO,
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InstrItinClass Itin = NoItinerary> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
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!strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
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class LogicRMM16<string opstr, RegisterOperand RO,
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InstrItinClass Itin = NoItinerary,
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SDPatternOperator OpNode = null_frag> :
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MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
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!strconcat(opstr, "\t$rt, $rs"),
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[(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
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let isCommutable = 1;
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let Constraints = "$rt = $dst";
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}
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class NotMM16<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
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!strconcat(opstr, "\t$rt, $rs"),
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[(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
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class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
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InstrItinClass Itin = NoItinerary> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
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!strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
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class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
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InstrItinClass Itin, Operand MemOpnd> :
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MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMImm4";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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}
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class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
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SDPatternOperator OpNode, InstrItinClass Itin,
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Operand MemOpnd> :
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MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
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!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMImm4";
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let mayStore = 1;
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}
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class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
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Operand MemOpnd> :
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MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
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!strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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}
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class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
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Operand MemOpnd> :
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MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
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!strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
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let mayStore = 1;
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}
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class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
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Operand MemOpnd> :
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MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
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!strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
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let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
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let canFoldAsLoad = 1;
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let mayLoad = 1;
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}
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class AddImmUR2<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
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!strconcat(opstr, "\t$rd, $rs, $imm"),
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[], II_ADDIU, FrmR> {
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let isCommutable = 1;
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}
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class AddImmUS5<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
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!strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
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let Constraints = "$rd = $dst";
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}
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class AddImmUR1SP<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
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!strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
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class AddImmUSP<string opstr> :
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MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
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!strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
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class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
|
|
MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
|
|
[], II_MFHI_MFLO, FrmR> {
|
|
let Uses = [UseReg];
|
|
let hasSideEffects = 0;
|
|
}
|
|
|
|
class MoveMM16<string opstr, RegisterOperand RO>
|
|
: MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
|
|
!strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
|
|
let isReMaterializable = 1;
|
|
}
|
|
|
|
class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
|
|
!strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
|
|
let isReMaterializable = 1;
|
|
}
|
|
|
|
// 16-bit Jump and Link (Call)
|
|
class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
|
|
[(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
|
|
let isCall = 1;
|
|
let hasDelaySlot = 1;
|
|
let Defs = [RA];
|
|
}
|
|
|
|
// 16-bit Jump Reg
|
|
class JumpRegMM16<string opstr, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
|
|
[], II_JR, FrmR> {
|
|
let hasDelaySlot = 1;
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
}
|
|
|
|
// Base class for JRADDIUSP instruction.
|
|
class JumpRAddiuStackMM16 :
|
|
MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
|
|
[], II_JRADDIUSP, FrmR> {
|
|
let isTerminator = 1;
|
|
let isBarrier = 1;
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
}
|
|
|
|
// 16-bit Jump and Link (Call) - Short Delay Slot
|
|
class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
|
|
[], II_JALRS, FrmR> {
|
|
let isCall = 1;
|
|
let hasDelaySlot = 1;
|
|
let Defs = [RA];
|
|
}
|
|
|
|
// 16-bit Jump Register Compact - No delay slot
|
|
class JumpRegCMM16<string opstr, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
|
|
[], II_JRC, FrmR> {
|
|
let isTerminator = 1;
|
|
let isBarrier = 1;
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
}
|
|
|
|
// Break16 and Sdbbp16
|
|
class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
|
|
MicroMipsInst16<(outs), (ins uimm4:$code_),
|
|
!strconcat(opstr, "\t$code_"),
|
|
[], Itin, FrmOther>;
|
|
|
|
class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
|
|
MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
|
|
!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
let Defs = [AT];
|
|
}
|
|
|
|
// MicroMIPS Jump and Link (Call) - Short Delay Slot
|
|
let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
|
|
class JumpLinkMM<string opstr, DAGOperand opnd> :
|
|
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
|
|
[], II_JALS, FrmJ, opstr> {
|
|
let DecoderMethod = "DecodeJumpTargetMM";
|
|
}
|
|
|
|
class JumpLinkRegMM<string opstr, RegisterOperand RO>:
|
|
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
|
|
[], II_JALRS, FrmR>;
|
|
|
|
class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
|
|
RegisterOperand RO> :
|
|
InstSE<(outs), (ins RO:$rs, opnd:$offset),
|
|
!strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
|
|
}
|
|
|
|
class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
|
|
SDPatternOperator OpNode = null_frag> :
|
|
InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
|
|
!strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
|
|
|
|
class PrefetchIndexed<string opstr> :
|
|
InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
|
|
!strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
|
|
|
|
class AddImmUPC<string opstr, RegisterOperand RO> :
|
|
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
|
|
!strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
|
|
|
|
/// A list of registers used by load/store multiple instructions.
|
|
def RegListAsmOperand : AsmOperandClass {
|
|
let Name = "RegList";
|
|
let ParserMethod = "parseRegisterList";
|
|
}
|
|
|
|
def reglist : Operand<i32> {
|
|
let EncoderMethod = "getRegisterListOpValue";
|
|
let ParserMatchClass = RegListAsmOperand;
|
|
let PrintMethod = "printRegisterList";
|
|
let DecoderMethod = "DecodeRegListOperand";
|
|
}
|
|
|
|
def RegList16AsmOperand : AsmOperandClass {
|
|
let Name = "RegList16";
|
|
let ParserMethod = "parseRegisterList";
|
|
let PredicateMethod = "isRegList16";
|
|
let RenderMethod = "addRegListOperands";
|
|
}
|
|
|
|
def reglist16 : Operand<i32> {
|
|
let EncoderMethod = "getRegisterListOpValue16";
|
|
let DecoderMethod = "DecodeRegListOperand16";
|
|
let PrintMethod = "printRegisterList";
|
|
let ParserMatchClass = RegList16AsmOperand;
|
|
}
|
|
|
|
class StoreMultMM<string opstr,
|
|
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
|
|
InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
|
|
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class LoadMultMM<string opstr,
|
|
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
|
|
InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
|
|
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
|
|
let DecoderMethod = "DecodeMemMMImm12";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class StoreMultMM16<string opstr,
|
|
InstrItinClass Itin = NoItinerary,
|
|
ComplexPattern Addr = addr> :
|
|
MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
|
|
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
|
|
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
|
|
let mayStore = 1;
|
|
}
|
|
|
|
class LoadMultMM16<string opstr,
|
|
InstrItinClass Itin = NoItinerary,
|
|
ComplexPattern Addr = addr> :
|
|
MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
|
|
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
|
|
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class UncondBranchMM16<string opstr> :
|
|
MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
|
|
!strconcat(opstr, "\t$offset"),
|
|
[], II_B, FrmI> {
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let isBarrier = 1;
|
|
let hasDelaySlot = 1;
|
|
let Predicates = [RelocPIC, InMicroMips];
|
|
let Defs = [AT];
|
|
}
|
|
|
|
def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
|
|
ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
|
|
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
|
|
LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
|
|
def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
|
|
SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
|
|
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
|
|
SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
|
|
|
|
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
|
|
ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
|
|
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
|
|
LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
|
|
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
|
|
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
|
|
def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
|
|
mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
|
|
def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
|
|
LOAD_STORE_FM_MM16<0x1a>;
|
|
def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
|
|
II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
|
|
def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
|
|
II_SH, mem_mm_4_lsl1>,
|
|
LOAD_STORE_FM_MM16<0x2a>;
|
|
def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
|
|
mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
|
|
def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
|
|
LOAD_GP_FM_MM16<0x19>;
|
|
def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
|
|
LOAD_STORE_SP_FM_MM16<0x12>;
|
|
def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
|
|
LOAD_STORE_SP_FM_MM16<0x32>;
|
|
def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
|
|
def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
|
|
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
|
|
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
|
|
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
|
|
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
|
|
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
|
|
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
|
|
IsAsCheapAsAMove;
|
|
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
|
|
def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
|
|
def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
|
|
def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
|
|
def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
|
|
BEQNEZ_FM_MM16<0x23>;
|
|
def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
|
|
BEQNEZ_FM_MM16<0x2b>;
|
|
def B16_MM : UncondBranchMM16<"b16">, B16_FM;
|
|
def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
|
|
ISA_MICROMIPS_NOT_32R6;
|
|
|
|
let DecoderNamespace = "MicroMips" in {
|
|
/// Load and Store Instructions - multiple
|
|
def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
let AdditionalPredicates = [InMicroMips] in {
|
|
def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
|
|
"cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
|
|
POOL32A_CFTC2_FM_MM<0b1100110100>;
|
|
def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
|
|
"ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
|
|
POOL32A_CFTC2_FM_MM<0b1101110100>;
|
|
}
|
|
}
|
|
|
|
class WaitMM<string opstr> :
|
|
InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
|
|
II_WAIT, FrmOther, opstr>;
|
|
|
|
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6,
|
|
NotMips64r6] in {
|
|
/// Compact Branch Instructions
|
|
def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
|
|
COMPACT_BRANCH_FM_MM<0x7>;
|
|
def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
|
|
COMPACT_BRANCH_FM_MM<0x5>;
|
|
}
|
|
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
|
/// Arithmetic Instructions (ALU Immediate)
|
|
def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
|
|
ADDI_FM_MM<0xc>;
|
|
def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
|
|
ADDI_FM_MM<0x4>;
|
|
def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
|
|
SLTI_FM_MM<0x24>;
|
|
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
|
|
SLTI_FM_MM<0x2c>;
|
|
def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
|
|
ADDI_FM_MM<0x34>;
|
|
def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
|
|
or>, ADDI_FM_MM<0x14>;
|
|
def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
|
|
immZExt16, xor>, ADDI_FM_MM<0x1c>;
|
|
def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM;
|
|
|
|
def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
|
|
LW_FM_MM<0xc>;
|
|
|
|
/// Arithmetic Instructions (3-Operand, R-Type)
|
|
def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
|
|
ADD_FM_MM<0, 0x150>;
|
|
def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
|
|
ADD_FM_MM<0, 0x1d0>;
|
|
def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>,
|
|
ADD_FM_MM<0, 0x210>;
|
|
def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
|
|
ADD_FM_MM<0, 0x110>;
|
|
def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
|
|
ADD_FM_MM<0, 0x190>;
|
|
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
|
|
def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
|
|
ADD_FM_MM<0, 0x390>;
|
|
def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
|
|
ADD_FM_MM<0, 0x250>;
|
|
def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
|
|
ADD_FM_MM<0, 0x290>;
|
|
def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
|
|
ADD_FM_MM<0, 0x310>;
|
|
def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
|
|
def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
|
|
MULT_FM_MM<0x22c>;
|
|
def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
|
|
MULT_FM_MM<0x26c>;
|
|
def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
|
|
MULT_FM_MM<0x2ac>, ISA_MIPS1_NOT_32R6_64R6;
|
|
def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
|
|
MULT_FM_MM<0x2ec>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
|
/// Arithmetic Instructions with PC and Immediate
|
|
def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
|
|
|
|
/// Shift Instructions
|
|
def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
|
|
SRA_FM_MM<0, 0>;
|
|
def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
|
|
SRA_FM_MM<0x40, 0>;
|
|
def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
|
|
SRA_FM_MM<0x80, 0>;
|
|
def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
|
|
SRLV_FM_MM<0x10, 0>;
|
|
def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
|
|
SRLV_FM_MM<0x50, 0>;
|
|
def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
|
|
SRLV_FM_MM<0x90, 0>;
|
|
def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
|
|
SRA_FM_MM<0xc0, 0> {
|
|
list<dag> Pattern = [(set GPR32Opnd:$rd,
|
|
(rotr GPR32Opnd:$rt, immZExt5:$shamt))];
|
|
}
|
|
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
|
|
SRLV_FM_MM<0xd0, 0> {
|
|
list<dag> Pattern = [(set GPR32Opnd:$rd,
|
|
(rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
|
|
}
|
|
|
|
/// Load and Store Instructions - aligned
|
|
let DecoderMethod = "DecodeMemMMImm16" in {
|
|
def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>,
|
|
MMRel, LW_FM_MM<0x7>;
|
|
def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>,
|
|
MMRel, LW_FM_MM<0x5>;
|
|
def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
|
|
addrDefault>, MMRel, LW_FM_MM<0xf>;
|
|
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
|
|
MMRel, LW_FM_MM<0xd>;
|
|
def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>;
|
|
def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel,
|
|
LW_FM_MM<0x6>;
|
|
def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel,
|
|
LW_FM_MM<0xe>;
|
|
def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
|
|
LW_FM_MM<0x3e>;
|
|
}
|
|
|
|
let DecoderMethod = "DecodeMemMMImm9" in {
|
|
def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
|
|
def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
|
|
def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9,
|
|
null_frag, II_LHE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
|
|
def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9,
|
|
null_frag, II_LHUE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
|
|
def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9,
|
|
null_frag, II_LWE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
|
|
def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9,
|
|
null_frag, II_SBE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
|
|
def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9,
|
|
null_frag, II_SHE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
|
|
def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9,
|
|
null_frag, II_SWE>,
|
|
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
|
|
}
|
|
|
|
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
|
|
|
|
/// Load and Store Instructions - unaligned
|
|
def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12, II_LWL>,
|
|
LWL_FM_MM<0x0>;
|
|
def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12, II_LWR>,
|
|
LWL_FM_MM<0x1>;
|
|
def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12, II_SWL>,
|
|
LWL_FM_MM<0x8>;
|
|
def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
|
|
LWL_FM_MM<0x9>;
|
|
let DecoderMethod = "DecodeMemMMImm9" in {
|
|
def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
|
|
II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
|
|
def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
|
|
II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
|
|
def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
|
|
II_SWLE>,
|
|
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
|
|
def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
|
|
II_SWRE>,
|
|
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
}
|
|
|
|
/// Load and Store Instructions - multiple
|
|
def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
|
|
def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>;
|
|
|
|
/// Load and Store Pair Instructions
|
|
def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>;
|
|
def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
|
|
|
|
/// Load and Store multiple pseudo Instructions
|
|
class LoadWordMultMM<string instr_asm > :
|
|
MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr")> ;
|
|
|
|
class StoreWordMultMM<string instr_asm > :
|
|
MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr")> ;
|
|
|
|
|
|
def SWM_MM : StoreWordMultMM<"swm">;
|
|
def LWM_MM : LoadWordMultMM<"lwm">;
|
|
|
|
/// Move Conditional
|
|
def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
|
|
NoItinerary>, ADD_FM_MM<0, 0x58>;
|
|
def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
|
|
NoItinerary>, ADD_FM_MM<0, 0x18>;
|
|
def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
|
|
CMov_F_I_FM_MM<0x25>;
|
|
def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
|
|
CMov_F_I_FM_MM<0x5>;
|
|
|
|
/// Move to/from HI/LO
|
|
def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
|
|
MTLO_FM_MM<0x0b5>;
|
|
def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
|
|
MTLO_FM_MM<0x0f5>;
|
|
def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
|
|
MFLO_FM_MM<0x035>;
|
|
def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
|
|
MFLO_FM_MM<0x075>;
|
|
|
|
/// Multiply Add/Sub Instructions
|
|
def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
|
|
def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
|
|
def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
|
|
def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
|
|
|
|
/// Count Leading
|
|
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
|
|
ISA_MIPS32;
|
|
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
|
|
ISA_MIPS32;
|
|
|
|
/// Sign Ext In Register Instructions.
|
|
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
|
|
SEB_FM_MM<0x0ac>, ISA_MIPS32R2;
|
|
def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
|
|
SEB_FM_MM<0x0ec>, ISA_MIPS32R2;
|
|
|
|
/// Word Swap Bytes Within Halfwords
|
|
def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
|
|
SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
|
|
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
|
|
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
|
|
immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
|
|
def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
|
|
immZExt5, immZExt5Plus1>,
|
|
EXT_FM_MM<0x0c>;
|
|
|
|
/// Jump Instructions
|
|
}
|
|
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in
|
|
def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
|
|
J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
|
|
IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
|
|
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
|
let DecoderMethod = "DecodeJumpTargetMM" in {
|
|
def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
|
|
def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>;
|
|
}
|
|
def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
|
|
|
|
/// Jump Instructions - Short Delay Slot
|
|
def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>;
|
|
def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>;
|
|
|
|
/// Branch Instructions
|
|
def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
|
|
BEQ_FM_MM<0x25>;
|
|
def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
|
|
BEQ_FM_MM<0x2d>;
|
|
def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
|
|
BGEZ_FM_MM<0x2>;
|
|
def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
|
|
BGEZ_FM_MM<0x6>;
|
|
def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
|
|
BGEZ_FM_MM<0x4>;
|
|
def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
|
|
BGEZ_FM_MM<0x0>;
|
|
def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
|
|
BGEZAL_FM_MM<0x03>;
|
|
def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
|
|
BGEZAL_FM_MM<0x01>;
|
|
|
|
/// Branch Instructions - Short Delay Slot
|
|
def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
|
|
GPR32Opnd>, BGEZAL_FM_MM<0x13>;
|
|
def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
|
|
GPR32Opnd>, BGEZAL_FM_MM<0x11>;
|
|
}
|
|
def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch, ISA_MICROMIPS;
|
|
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
|
|
|
|
/// Control Instructions
|
|
def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
|
|
def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM;
|
|
def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
|
|
def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
|
|
def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
|
|
def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
|
|
def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
|
|
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
|
|
ISA_MIPS32R2;
|
|
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
|
|
ISA_MIPS32R2;
|
|
|
|
/// Trap Instructions
|
|
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>;
|
|
def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>;
|
|
def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
|
|
TEQ_FM_MM<0x10>;
|
|
def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>;
|
|
def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
|
|
TEQ_FM_MM<0x28>;
|
|
def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>;
|
|
|
|
def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>;
|
|
def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>;
|
|
def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
|
|
TEQI_FM_MM<0x0b>;
|
|
def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>;
|
|
def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
|
|
TEQI_FM_MM<0x0a>;
|
|
def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>;
|
|
|
|
/// Load-linked, Store-conditional
|
|
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
|
|
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
|
|
|
|
def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
|
|
def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
|
|
|
|
let DecoderMethod = "DecodeCacheOpMM" in {
|
|
def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
|
|
CACHE_PREF_FM_MM<0x08, 0x6>;
|
|
def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
|
|
CACHE_PREF_FM_MM<0x18, 0x2>;
|
|
}
|
|
|
|
let DecoderMethod = "DecodePrefeOpMM" in {
|
|
def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
|
|
CACHE_PREFE_FM_MM<0x18, 0x2>;
|
|
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
|
|
CACHE_PREFE_FM_MM<0x18, 0x3>;
|
|
}
|
|
def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
|
|
def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
|
|
def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
|
|
|
|
def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>;
|
|
def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>;
|
|
def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>;
|
|
def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>;
|
|
|
|
def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM;
|
|
|
|
def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
|
|
}
|
|
|
|
def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
|
def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
|
|
def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
|
|
let DecoderNamespace = "MicroMips" in {
|
|
def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
|
|
RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
|
|
mem_simm12>, LL_FM_MM<0xe>,
|
|
ISA_MICROMIPS32_NOT_MIPS32R6;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MicroMips arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let AdditionalPredicates = [InMicroMips] in {
|
|
def : MipsPat<(i32 immLi16:$imm),
|
|
(LI16_MM immLi16:$imm)>;
|
|
|
|
defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
|
|
}
|
|
|
|
let Predicates = [InMicroMips] in {
|
|
def : MipsPat<(not GPRMM16:$in),
|
|
(NOT16_MM GPRMM16:$in)>;
|
|
def : MipsPat<(not GPR32:$in),
|
|
(NOR_MM GPR32Opnd:$in, ZERO)>;
|
|
|
|
def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
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(ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
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def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
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(ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
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def : MipsPat<(add GPR32:$src, immSExt16:$imm),
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(ADDiu_MM GPR32:$src, immSExt16:$imm)>;
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def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
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(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
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def : MipsPat<(and GPR32:$src, immZExt16:$imm),
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(ANDi_MM GPR32:$src, immZExt16:$imm)>;
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def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
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(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
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def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
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(SLL_MM GPR32:$src, immZExt5:$imm)>;
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def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
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(SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
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def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
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(SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
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def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
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(SRL_MM GPR32:$src, immZExt5:$imm)>;
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def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
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(SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
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def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
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(SRA_MM GPR32:$src, immZExt5:$imm)>;
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def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
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(SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
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def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
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(SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
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def : MipsPat<(store GPR32:$src, addr:$addr),
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(SW_MM GPR32:$src, addr:$addr)>;
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def : MipsPat<(load addrimm4lsl2:$addr),
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(LW16_MM addrimm4lsl2:$addr)>;
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def : MipsPat<(load addr:$addr),
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(LW_MM addr:$addr)>;
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def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
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(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
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}
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def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
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(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
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(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
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|
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let AddedComplexity = 40 in {
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def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
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(LH_MM addrRegImm:$a)>;
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}
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def : MipsPat<(atomic_load_16 addr:$a),
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(LH_MM addr:$a)>;
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def : MipsPat<(i32 (extloadi16 addr:$src)),
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|
(LHu_MM addr:$src)>;
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|
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defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
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SLTiu_MM, ZERO>;
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defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
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defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
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defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
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defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
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defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
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|
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//===----------------------------------------------------------------------===//
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// MicroMips instruction aliases
|
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//===----------------------------------------------------------------------===//
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class UncondBranchMMPseudo<string opstr> :
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MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
|
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!strconcat(opstr, "\t$offset")>;
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|
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def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
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|
|
|
let Predicates = [InMicroMips] in {
|
|
def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
|
|
II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
|
|
II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
|
|
|
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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|
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
|
|
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
|
|
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
|
|
def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
|
|
def : MipsInstAlias<"teq $rs, $rt",
|
|
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<"tge $rs, $rt",
|
|
(TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<"tgeu $rs, $rt",
|
|
(TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<"tlt $rs, $rt",
|
|
(TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<"tltu $rs, $rt",
|
|
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<"tne $rs, $rt",
|
|
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
|
|
def : MipsInstAlias<
|
|
"sgt $rd, $rs, $rt",
|
|
(SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<
|
|
"sgt $rs, $rt",
|
|
(SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<
|
|
"sgtu $rd, $rs, $rt",
|
|
(SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<
|
|
"sgtu $rs, $rt",
|
|
(SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<"sll $rd, $rt, $rs",
|
|
(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<"sra $rd, $rt, $rs",
|
|
(SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<"srl $rd, $rt, $rs",
|
|
(SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
|
|
def : MipsInstAlias<"sll $rd, $rt",
|
|
(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
|
def : MipsInstAlias<"sra $rd, $rt",
|
|
(SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
|
def : MipsInstAlias<"srl $rd, $rt",
|
|
(SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
|
def : MipsInstAlias<"sll $rd, $shamt",
|
|
(SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
|
|
def : MipsInstAlias<"sra $rd, $shamt",
|
|
(SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
|
|
def : MipsInstAlias<"srl $rd, $shamt",
|
|
(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
|
|
def : MipsInstAlias<"rotr $rt, $imm",
|
|
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
|
|
def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>;
|
|
|
|
defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>;
|
|
|
|
def : MipsInstAlias<"not $rt, $rs",
|
|
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
|
|
def : MipsInstAlias<"not $rt",
|
|
(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
|
|
def : MipsInstAlias<"bnez $rs,$offset",
|
|
(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
def : MipsInstAlias<"beqz $rs,$offset",
|
|
(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
|
|
def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
|
|
ISA_MIPS32R2_NOT_32R6_64R6;
|
|
def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
|
|
ISA_MIPS32R2_NOT_32R6_64R6;
|
|
}
|