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https://github.com/RPCS3/llvm-mirror.git
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50947152c2
Summary of changes: - added description of MTBUF instructions and format modifier; - described limitations of f16 inline constants when used with integer operands; - updated description of gfx9+ flat global addressing modes; - v_accvgpr_write_b32 src0 corrections (gfx908); - minor bugfixing and improvements.
82 lines
3.4 KiB
ReStructuredText
82 lines
3.4 KiB
ReStructuredText
..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid10_hwreg:
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hwreg
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===========================
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Bits of a hardware register being accessed.
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The bits of this operand have the following meaning:
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======= ===================== ============
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Bits Description Value Range
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======= ===================== ============
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5:0 Register *id*. 0..63
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10:6 First bit *offset*. 0..31
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15:11 *Size* in bits. 1..32
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======= ===================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* An *hwreg* value described below.
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==================================== ============================================================================
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Hwreg Value Syntax Description
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==================================== ============================================================================
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hwreg({0..63}) All bits of a register indicated by its *id*.
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hwreg(<*name*>) All bits of a register indicated by its *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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==================================== ============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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=================== ==========================================
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Name Description
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=================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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HW_REG_XNACK_MASK xnack_mask register.
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HW_REG_POPS_PACKER pops_packer register.
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=================== ==========================================
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Examples:
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.. parsed-literal::
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reg = 1
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offset = 2
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size = 4
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hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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s_getreg_b32 s2, 0x1881
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s_getreg_b32 s2, hwreg_enc // the same as above
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s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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s_getreg_b32 s2, hwreg(15)
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s_getreg_b32 s2, hwreg(51, 1, 31)
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s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
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