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https://github.com/RPCS3/llvm-mirror.git
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301 lines
8.1 KiB
C++
301 lines
8.1 KiB
C++
//===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC_FRAMEINFO_H
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#define POWERPC_FRAMEINFO_H
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#include "PPC.h"
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#include "PPCSubtarget.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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namespace llvm {
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class PPCFrameInfo: public TargetFrameInfo {
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const TargetMachine &TM;
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public:
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PPCFrameInfo(const TargetMachine &tm, bool LP64)
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: TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
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}
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/// getReturnSaveOffset - Return the previous frame offset to save the
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/// return address.
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static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
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if (isDarwinABI)
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return isPPC64 ? 16 : 8;
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// SVR4 ABI:
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return isPPC64 ? 16 : 4;
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}
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/// getFramePointerSaveOffset - Return the previous frame offset to save the
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/// frame pointer.
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static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
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// For the Darwin ABI:
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// We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
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// for saving the frame pointer (if needed.) While the published ABI has
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// not used this slot since at least MacOSX 10.2, there is older code
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// around that does use it, and that needs to continue to work.
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if (isDarwinABI)
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return isPPC64 ? -8U : -4U;
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// SVR4 ABI: First slot in the general register save area.
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return -4U;
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}
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/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
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///
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static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
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if (isDarwinABI || isPPC64)
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return 6 * (isPPC64 ? 8 : 4);
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// SVR4 ABI:
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return 8;
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}
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/// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
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/// argument area.
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static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
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// For the Darwin ABI / 64-bit SVR4 ABI:
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// The prolog code of the callee may store up to 8 GPR argument registers to
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// the stack, allowing va_start to index over them in memory if its varargs.
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// Because we cannot tell if this is needed on the caller side, we have to
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// conservatively assume that it is needed. As such, make sure we have at
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// least enough stack space for the caller to store the 8 GPRs.
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if (isDarwinABI || isPPC64)
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return 8 * (isPPC64 ? 8 : 4);
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// 32-bit SVR4 ABI:
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// There is no default stack allocated for the 8 first GPR arguments.
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return 0;
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}
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/// getMinCallFrameSize - Return the minimum size a call frame can be using
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/// the PowerPC ABI.
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static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
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// The call frame needs to be at least big enough for linkage and 8 args.
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return getLinkageSize(isPPC64, isDarwinABI) +
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getMinCallArgumentsSize(isPPC64, isDarwinABI);
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}
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// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
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const SpillSlot *
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getCalleeSavedSpillSlots(unsigned &NumEntries) const {
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if (TM.getSubtarget<PPCSubtarget>().isDarwinABI()) {
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NumEntries = 1;
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if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
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static const SpillSlot darwin64Offsets = {PPC::X31, -8};
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return &darwin64Offsets;
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} else {
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static const SpillSlot darwinOffsets = {PPC::R31, -4};
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return &darwinOffsets;
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}
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}
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// Early exit if not using the SVR4 ABI.
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if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
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NumEntries = 0;
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return 0;
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}
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static const SpillSlot Offsets[] = {
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// Floating-point register save area offsets.
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{PPC::F31, -8},
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{PPC::F30, -16},
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{PPC::F29, -24},
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{PPC::F28, -32},
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{PPC::F27, -40},
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{PPC::F26, -48},
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{PPC::F25, -56},
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{PPC::F24, -64},
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{PPC::F23, -72},
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{PPC::F22, -80},
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{PPC::F21, -88},
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{PPC::F20, -96},
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{PPC::F19, -104},
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{PPC::F18, -112},
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{PPC::F17, -120},
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{PPC::F16, -128},
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{PPC::F15, -136},
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{PPC::F14, -144},
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// General register save area offsets.
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{PPC::R31, -4},
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{PPC::R30, -8},
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{PPC::R29, -12},
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{PPC::R28, -16},
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{PPC::R27, -20},
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{PPC::R26, -24},
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{PPC::R25, -28},
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{PPC::R24, -32},
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{PPC::R23, -36},
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{PPC::R22, -40},
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{PPC::R21, -44},
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{PPC::R20, -48},
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{PPC::R19, -52},
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{PPC::R18, -56},
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{PPC::R17, -60},
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{PPC::R16, -64},
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{PPC::R15, -68},
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{PPC::R14, -72},
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// CR save area offset.
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// FIXME SVR4: Disable CR save area for now.
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// {PPC::CR2, -4},
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// {PPC::CR3, -4},
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// {PPC::CR4, -4},
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// {PPC::CR2LT, -4},
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// {PPC::CR2GT, -4},
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// {PPC::CR2EQ, -4},
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// {PPC::CR2UN, -4},
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// {PPC::CR3LT, -4},
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// {PPC::CR3GT, -4},
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// {PPC::CR3EQ, -4},
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// {PPC::CR3UN, -4},
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// {PPC::CR4LT, -4},
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// {PPC::CR4GT, -4},
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// {PPC::CR4EQ, -4},
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// {PPC::CR4UN, -4},
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// VRSAVE save area offset.
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{PPC::VRSAVE, -4},
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// Vector register save area
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{PPC::V31, -16},
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{PPC::V30, -32},
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{PPC::V29, -48},
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{PPC::V28, -64},
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{PPC::V27, -80},
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{PPC::V26, -96},
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{PPC::V25, -112},
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{PPC::V24, -128},
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{PPC::V23, -144},
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{PPC::V22, -160},
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{PPC::V21, -176},
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{PPC::V20, -192}
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};
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static const SpillSlot Offsets64[] = {
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// Floating-point register save area offsets.
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{PPC::F31, -8},
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{PPC::F30, -16},
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{PPC::F29, -24},
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{PPC::F28, -32},
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{PPC::F27, -40},
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{PPC::F26, -48},
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{PPC::F25, -56},
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{PPC::F24, -64},
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{PPC::F23, -72},
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{PPC::F22, -80},
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{PPC::F21, -88},
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{PPC::F20, -96},
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{PPC::F19, -104},
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{PPC::F18, -112},
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{PPC::F17, -120},
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{PPC::F16, -128},
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{PPC::F15, -136},
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{PPC::F14, -144},
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// General register save area offsets.
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// FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit
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// mode?
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{PPC::R31, -4},
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{PPC::R30, -12},
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{PPC::R29, -20},
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{PPC::R28, -28},
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{PPC::R27, -36},
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{PPC::R26, -44},
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{PPC::R25, -52},
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{PPC::R24, -60},
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{PPC::R23, -68},
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{PPC::R22, -76},
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{PPC::R21, -84},
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{PPC::R20, -92},
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{PPC::R19, -100},
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{PPC::R18, -108},
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{PPC::R17, -116},
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{PPC::R16, -124},
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{PPC::R15, -132},
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{PPC::R14, -140},
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{PPC::X31, -8},
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{PPC::X30, -16},
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{PPC::X29, -24},
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{PPC::X28, -32},
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{PPC::X27, -40},
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{PPC::X26, -48},
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{PPC::X25, -56},
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{PPC::X24, -64},
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{PPC::X23, -72},
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{PPC::X22, -80},
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{PPC::X21, -88},
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{PPC::X20, -96},
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{PPC::X19, -104},
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{PPC::X18, -112},
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{PPC::X17, -120},
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{PPC::X16, -128},
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{PPC::X15, -136},
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{PPC::X14, -144},
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// CR save area offset.
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// FIXME SVR4: Disable CR save area for now.
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// {PPC::CR2, -4},
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// {PPC::CR3, -4},
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// {PPC::CR4, -4},
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// {PPC::CR2LT, -4},
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// {PPC::CR2GT, -4},
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// {PPC::CR2EQ, -4},
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// {PPC::CR2UN, -4},
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// {PPC::CR3LT, -4},
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// {PPC::CR3GT, -4},
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// {PPC::CR3EQ, -4},
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// {PPC::CR3UN, -4},
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// {PPC::CR4LT, -4},
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// {PPC::CR4GT, -4},
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// {PPC::CR4EQ, -4},
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// {PPC::CR4UN, -4},
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// VRSAVE save area offset.
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{PPC::VRSAVE, -4},
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// Vector register save area
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{PPC::V31, -16},
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{PPC::V30, -32},
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{PPC::V29, -48},
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{PPC::V28, -64},
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{PPC::V27, -80},
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{PPC::V26, -96},
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{PPC::V25, -112},
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{PPC::V24, -128},
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{PPC::V23, -144},
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{PPC::V22, -160},
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{PPC::V21, -176},
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{PPC::V20, -192}
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};
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if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
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NumEntries = array_lengthof(Offsets64);
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return Offsets64;
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} else {
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NumEntries = array_lengthof(Offsets);
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return Offsets;
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}
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}
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};
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} // End llvm namespace
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#endif
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