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5867567c41
Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
242 lines
8.5 KiB
LLVM
242 lines
8.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_uqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_uqadd_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: uqadd v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @test_sqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_sqadd_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: sqadd v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_uqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_uqadd_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: uqadd v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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define <16 x i8> @test_sqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_sqadd_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: sqadd v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>)
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define <4 x i16> @test_uqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_uqadd_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: uqadd v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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define <4 x i16> @test_sqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_sqadd_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: sqadd v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_uqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_uqadd_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: uqadd v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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define <8 x i16> @test_sqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_sqadd_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: sqadd v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>)
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declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_uqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_uqadd_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: uqadd v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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define <2 x i32> @test_sqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_sqadd_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: sqadd v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_uqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_uqadd_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: uqadd v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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define <4 x i32> @test_sqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_sqadd_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: sqadd v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>)
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define <2 x i64> @test_uqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
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; CHECK: test_uqadd_v2i64:
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%tmp1 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
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; CHECK: uqadd v0.2d, v0.2d, v1.2d
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ret <2 x i64> %tmp1
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}
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define <2 x i64> @test_sqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
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; CHECK: test_sqadd_v2i64:
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%tmp1 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
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; CHECK: sqadd v0.2d, v0.2d, v1.2d
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ret <2 x i64> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>)
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declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_uqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_uqsub_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: uqsub v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @test_sqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
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; CHECK: test_sqsub_v8i8:
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%tmp1 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
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; CHECK: sqsub v0.8b, v0.8b, v1.8b
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ret <8 x i8> %tmp1
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}
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declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>)
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declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_uqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_uqsub_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: uqsub v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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define <16 x i8> @test_sqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
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; CHECK: test_sqsub_v16i8:
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%tmp1 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
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; CHECK: sqsub v0.16b, v0.16b, v1.16b
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ret <16 x i8> %tmp1
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}
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declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>)
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declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>)
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define <4 x i16> @test_uqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_uqsub_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: uqsub v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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define <4 x i16> @test_sqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
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; CHECK: test_sqsub_v4i16:
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%tmp1 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
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; CHECK: sqsub v0.4h, v0.4h, v1.4h
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ret <4 x i16> %tmp1
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}
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declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_uqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_uqsub_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: uqsub v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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define <8 x i16> @test_sqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
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; CHECK: test_sqsub_v8i16:
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%tmp1 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
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; CHECK: sqsub v0.8h, v0.8h, v1.8h
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ret <8 x i16> %tmp1
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}
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declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>)
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declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>)
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define <2 x i32> @test_uqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_uqsub_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: uqsub v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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define <2 x i32> @test_sqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK: test_sqsub_v2i32:
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%tmp1 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
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; CHECK: sqsub v0.2s, v0.2s, v1.2s
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ret <2 x i32> %tmp1
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}
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declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_uqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_uqsub_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: uqsub v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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define <4 x i32> @test_sqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
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; CHECK: test_sqsub_v4i32:
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%tmp1 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
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; CHECK: sqsub v0.4s, v0.4s, v1.4s
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ret <4 x i32> %tmp1
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}
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declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>)
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declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>)
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define <2 x i64> @test_uqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
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; CHECK: test_uqsub_v2i64:
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%tmp1 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
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; CHECK: uqsub v0.2d, v0.2d, v1.2d
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ret <2 x i64> %tmp1
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}
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define <2 x i64> @test_sqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
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; CHECK: test_sqsub_v2i64:
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%tmp1 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
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; CHECK: sqsub v0.2d, v0.2d, v1.2d
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ret <2 x i64> %tmp1
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}
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