1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/include/llvm/Target
Gerolf Hoflehner fbd25ba142 [AAarch64] Optimize CSINC-branch sequence
Peephole optimization that generates a single conditional branch
for csinc-branch sequences like in the examples below. This is
possible when the csinc sets or clears a register based on a condition
code and the branch checks that register. Also the condition
code may not be modified between the csinc and the original branch.

Examples:

1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44
   to b.<invCC>

2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44
   to b.<CC>


rdar://problem/18506500

llvm-svn: 219742
2014-10-14 23:07:53 +00:00
..
CostTable.h
Target.td Remove unused field from Operand 2014-10-09 19:15:18 +00:00
TargetCallingConv.h
TargetCallingConv.td [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values. 2014-09-25 12:15:05 +00:00
TargetFrameLowering.h Re-apply r211399, "Generate native unwind info on Win64" with a fix to ignore SEH pseudo ops in X86 JIT emitter. 2014-06-25 12:41:52 +00:00
TargetInstrInfo.h [AAarch64] Optimize CSINC-branch sequence 2014-10-14 23:07:53 +00:00
TargetIntrinsicInfo.h Trailing whitespace. 2014-07-23 00:42:52 +00:00
TargetItinerary.td
TargetLibraryInfo.h PR21145: Teach LLVM about C++14 sized deallocation functions. 2014-10-03 20:17:06 +00:00
TargetLowering.h [DAGCombine] Remove SIGN_EXTEND-related inf-loop 2014-10-06 20:19:47 +00:00
TargetLoweringObjectFile.h CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF 2014-07-14 22:57:27 +00:00
TargetMachine.h Target: Fix build breakage. 2014-09-26 02:57:05 +00:00
TargetOpcodes.h [stack protector] Fix a potential security bug in stack protector where the 2014-07-25 19:31:34 +00:00
TargetOptions.h Satiate the sanitizer build bot 2014-08-21 20:09:15 +00:00
TargetRegisterInfo.h Revert 202433 - Provide a target override for the latest regalloc heuristic 2014-10-03 12:20:53 +00:00
TargetSchedule.td Move Post RA Scheduling flag bit into SchedMachineModel 2014-07-15 22:39:58 +00:00
TargetSelectionDAG.td Add SDAG TableGen definitions for BR_CC 2014-09-25 23:34:18 +00:00
TargetSelectionDAGInfo.h Trailing whitespace. 2014-07-23 00:42:52 +00:00
TargetSubtargetInfo.h [PBQP] Replace PBQPBuilder with composable constraints (PBQPRAConstraint). 2014-10-09 18:20:51 +00:00