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fbd25ba142
Peephole optimization that generates a single conditional branch for csinc-branch sequences like in the examples below. This is possible when the csinc sets or clears a register based on a condition code and the branch checks that register. Also the condition code may not be modified between the csinc and the original branch. Examples: 1. Convert csinc w9, wzr, wzr, <CC>;tbnz w9, #0, 0x44 to b.<invCC> 2. Convert csinc w9, wzr, wzr, <CC>; tbz w9, #0, 0x44 to b.<CC> rdar://problem/18506500 llvm-svn: 219742
27 lines
711 B
LLVM
27 lines
711 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwint | FileCheck %s
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; Checks for conditional branch b.vs
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; Function Attrs: nounwind
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define i32 @add(i32, i32) {
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entry:
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%2 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %0, i32 %1)
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%3 = extractvalue { i32, i1 } %2, 1
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br i1 %3, label %6, label %4
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; <label>:4 ; preds = %entry
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%5 = extractvalue { i32, i1 } %2, 0
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ret i32 %5
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; <label>:6 ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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; CHECK: b.vs
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}
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; Function Attrs: nounwind readnone
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32)
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap()
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